Datasheet
LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 8 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
PIO0_4/ADC_11/
TRSTN/WAKEUP
64
[3]
I; PU IO PIO0_4 — General-purpose port 0 input/output 4.
In boundary scan mode: TRST (Test Reset).
In ISP mode, this pin is the U0_TXD pin.
This pin triggers a wake-up from Deep power-down mode. If the
part must wake up from Deep power-down mode via an external
pin, do not assign any movable function to this pin. This pin
should be pulled HIGH externally before entering Deep
power-down mode. A LOW-going pulse as short as 50 ns causes
the chip to exit Deep power-down mode and wakes up the part.
A ADC_11 — ADC input 11.
RESET
/PIO0_5 5 3
[7]
I; PU IO RESET — External reset input: A LOW-going pulse as short as
50 ns on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor
execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET
pin can be left unconnected or be used as
a GPIO or for any movable function if an external RESET function
is not needed and the Deep power-down mode is not used.
I PIO0_5 — General-purpose port 0 input/output 5.
PIO0_6/ADC_1/
VDDCMP
-23
[10]
I; PU IO PIO0_6 — General-purpose port 0 input/output 6.
A ADC_1 — ADC input 1.
A VDDCMP — Alternate reference voltage for the analog
comparator.
PIO0_7/ADC_0 - 22
[2]
I; PU IO PIO0_7 — General-purpose port 0 input/output 7.
A ADC_0 — ADC input 0.
PIO0_8/XTALIN 14 18
[8]
I; PU IO PIO0_8 — General-purpose port 0 input/output 8.
A XTALIN — Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed 1.95 V.
PIO0_9/XTALOUT 13 17
[8]
I; PU IO PIO0_9 — General-purpose port 0 input/output 9.
A XTALOUT — Output from the oscillator circuit.
PIO0_10/I2C0_SCL 10 9
[6]
Inactive I; F PIO0_10 — General-purpose port 0 input/output 10 (open-drain).
I2C0_SCL — Open-drain I
2
C-bus clock input/output. High-current
sink if I
2
C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_11/I2C0_SDA 9 8
[6]
Inactive I; F PIO0_11 — General-purpose port 0 input/output 11 (open-drain).
I2C0_SDA — Open-drain I
2
C-bus data input/output. High-current
sink if I
2
C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_12 4 2
[4]
I; PU IO PIO0_12 — General-purpose port 0 input/output 12. ISP entry
pin. A LOW level on this pin during reset starts the ISP command
handler.
PIO0_13/ADC_10 3 1
[2]
I; PU IO PIO0_13 — General-purpose port 0 input/output 13.
A ADC_10 — ADC input 10.
Table 3. Pin description
Symbol
TSSOP20
HVQFN33
Reset
state
[1]
Type Description