Datasheet

LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 56 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
12.3.5 SPI interfaces
In master mode, the maximum supported bit rate is limited by the maximum system clock
to 30 Mbit/s. In slave mode, assuming a set-up time of 3 ns for the external device and
neglecting any PCB trace delays, the maximum supported bit rate is 1/(2 x (26 ns + 3 ns))
= 17 Mbit/s at 3.0 V <= VDD <= 3.6 V and 13 Mbit/s at 1.8 V <= VDD < 3.0 V. The actual
bit rate depends on the delays introduced by the external trace and the external device.
Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for
all digital pins except the open-drain pins PIO0_10 and PIO0_11.
Table 19. SPI dynamic characteristics
T
amb
=  40  C to 105  C; C
L
= 20 pF; input slew = 1 ns. Simulated parameters sampled at the 30 %
and 70 % level of the rising or falling edge; values guaranteed by design. Delays introduced by the
external trace or external device are not considered.
Symbol Parameter Conditions Min Max Unit
SPI master
t
DS
data set-up time 1.8 V <= V
DD
<= 3.6 V 2 - ns
t
DH
data hold time 1.8 V <= V
DD
<= 3.6 V 6 - ns
t
v(Q)
data output valid time 1.8 V <= V
DD
<= 3.6 V -3 4 ns
SPI slave
t
DS
data set-up time 1.8 V <= V
DD
<= 3.6 V 2 - ns
t
DH
data hold time 1.8 V <= V
DD
<= 3.6 V 4 - ns
t
v(Q)
data output valid time 3.0 V <= V
DD
<= 3.6 V 0 26 ns
1.8 V <= V
DD
< 3.0 V 0 35 ns