Datasheet

LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 45 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
11.5 CoreMark data
Conditions: V
DD
= 3.3 V; T
amb
= 25 °C; active mode; all peripherals except one UART and the SCT
disabled in the SYSAHBCLKCTRL register; BOD disabled; internal pull-up resistors enabled.
Measured with Keil uVision 5.10.
1 MHz - 6 MHz: external clock; IRC, PLL disabled.12 MHz: IRC enabled; PLL disabled. 24 MHz:
IRC enabled; PLL enabled.30 MHz: system oscillator enabled; PLL enabled.
Fig 23. CoreMark score
Conditions: V
DD
= 3.3 V; T
amb
= 25 °C; active mode; all peripherals except one UART and the SCT
disabled in the SYSAHBCLKCTRL register; BOD disabled; internal pull-up resistors enabled.
Measured with Keil uVision 5.10.
1 MHz - 6 MHz: external clock; IRC, PLL disabled.12 MHz: IRC enabled; PLL disabled.24 MHz:
IRC enabled; PLL enabled.30 MHz: system oscillator enabled; PLL enabled.
Fig 24. Active mode: CoreMark power consumption I
DD
aaa-014006
0 6 12 18 24 30
0
0.5
1
1.5
2
2.5
system clock frequency (MHz)
coremark scorecoremark scorecoremark score
((iterations/s)/MHz)((iterations/s)/MHz)((iterations/s)/MHz)
defaultdefaultdefault
CPU/efficiencyCPU/ef
ficiency
low-currentlow-currentlow-current
CPU performance/efficiency
aaa-014007
0 6 12 18 24 30
0
2
4
6
8
system clock frequency (MHz)
I
DD
DD
I
DD
(mA)
(mA)
(mA)
default
default
default
CPU/efficiency
CPU/efficiency
low-current
low-current
low-current
CPU performance/efficiency