Datasheet

LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 41 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
Conditions: V
DD
= 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz - 6 MHz: external clock; IRC, PLL disabled.
12 MHz: IRC enabled; PLL disabled.
24 MHz: IRC enabled; PLL enabled.
30 MHz: system oscillator enabled; PLL enabled.
Fig 15. Sleep mode: Typical supply current I
DD
versus temperature for different system
clock frequencies
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 16. Deep-sleep mode: Typical supply current I
DD
versus temperature for different
supply voltages V
DD
aaa-013994
-40 10 60 110
0
0.5
1
1.5
2
2.5
temperature (°C)
I
DD
DD
I
DD
(mA)
(mA)
(mA)
30 MHz
30 MHz
30 MHz
24 MHz
24 MHz
24 MHz
12 MHz
12 MHz
12 MHz
6 MHz
6 MHz
6 MHz
4 MHz
4 MHz
4 MHz
3 MHz
3 MHz
3 MHz
2 MHz
2 MHz
2 MHz
1 MHz
1 MHz
1 MHz
aaa-013983
-40 -10 20 50 80 110
120
130
140
150
160
170
180
temperature (°C)
I
DDDD
I
DD
(uA)(uA)(μA)
3.6 V3.6 VV
DD
= 3.6 V
3.3 V3.3 V3.3 V
2.7 V2.7 V2.7 V
2 V2 V2 V
1.8 V1.8 V1.8 V