Datasheet

LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 30 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
8.24 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is
configured to support up to four breakpoints and two watch points.
The Micro Trace Buffer is implemented on the LPC82x.
The RESET
pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET
= HIGH). The ARM SWD debug port is disabled while the LPC82x is
in reset. The JTAG boundary scan pins are selected by hardware when the part is in
boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 3
).
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET
pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET
pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST
pin to enable the
SWD debug mode, and release the RESET
pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
Fig 11. Connecting the SWD pins to a standard SWD connector
RESET
SWDIO
SWCLK
V
DD
LPC82x
ISP entry
PIO0_12
VTREF
SWDIO
SWCLK
nRESET
GND
aaa-015075
from SWD
connector
3.3 V
~10 kΩ -
100 kΩ
DGND
~10 kΩ -
100 kΩ