Datasheet

LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 12 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
8. Functional description
8.1 ARM Cortex-M0+ core
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a
two-stage pipeline. The core revision is r0p1.
Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two
watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast
GPIO access.
The core includes a single-cycle multiplier and a system tick timer.
8.2 On-chip flash program memory
The LPC82x contain up to 32 KB of on-chip flash program memory. The flash memory
supports a 64 Byte page size with page write and erase.
8.3 On-chip SRAM
The LPC82x contain a total of 8 KB on-chip static RAM data memory in two separate
SRAM blocks with one combined clock for both SRAM blocks.
8.4 On-chip ROM
The on-chip ROM contains the bootloader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
• APIs to use the following peripherals:
– SPI
– USART
– I2C
– ADC
8.5 Memory map
The LPC82x incorporates several distinct memory regions. Figure 6 shows the overall
map of the entire address space from the user program viewpoint following reset. The
interrupt vector area supports address remapping.
The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,
the system tick timer (SysTick), and the reduced power modes.