Datasheet

LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 1 — 1 October 2014 10 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. This pin is
active in Deep power-down mode and includes a 20 ns glitch filter (active in all power modes). In Deep power-down mode, pulling the
WAKEUP pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other purposes, if the WKT
low-power oscillator is enabled for waking up the part from Deep power-down mode. See Table 16 “
Dynamic characteristics:
WKTCLKIN pin” for the WKTCLKIN input.
[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[6] True open-drain pin. I
2
C-bus pins compliant with the I
2
C-bus specification for I
2
C standard mode, I
2
C Fast-mode, and I
2
C Fast-mode
Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output
functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all
functions on this pin.
[7] See Figure 10
for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is
not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An
external pull-up resistor is required on this pin for the Deep power-down mode.
[8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system
oscillator. When configured for XTALIN and XTALOUT, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[9] The WKTCLKIN function is enabled in the DPDCTRL register in the PMU. See the LPC82x user manual.
[10] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with
configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is
disabled.
Table 4. Movable functions (assign to pins PIO0_0 to PIO0_28 through switch matrix)
Function name Type Description
U0_TXD O Transmitter output for USART0.
U0_RXD I Receiver input for USART0.
U0_RTS
O Request To Send output for USART0.
U0_CTS
I Clear To Send input for USART0.
U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode.
U1_TXD O Transmitter output for USART1.
U1_RXD I Receiver input for USART1.
U1_RTS
O Request To Send output for USART1.
U1_CTS
I Clear To Send input for USART1.
U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode.
U2_TXD O Transmitter output for USART2.
U2_RXD I Receiver input for USART2.
U2_RTS
O Request To Send output for USART1.
U2_CTS
I Clear To Send input for USART1.
U2_SCLK I/O Serial clock input/output for USART1 in synchronous mode.
SPI0_SCK I/O Serial clock for SPI0.
SPI0_MOSI I/O Master Out Slave In for SPI0.
SPI0_MISO I/O Master In Slave Out for SPI0.
SPI0_SSEL0 I/O Slave select 0 for SPI0.
SPI0_SSEL1 I/O Slave select 0 for SPI1.
SPI0_SSEL2 I/O Slave select 0 for SPI2.
SPI0_SSEL3 I/O Slave select 0 for SPI3.
SPI1_SCK I/O Serial clock for SPI1.
SPI1_MOSI I/O Master Out Slave In for SPI1.