LPC82x 32-bit ARM Cortex-M0+ microcontroller; up to 32 kB flash and 8 kB SRAM; 12-bit ADC; comparator Rev. 1 — 1 October 2014 Product data sheet 1. General description The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and 8 KB of SRAM.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LPC82x Product data sheet High-current sink driver (20 mA) on two true open-drain pins. GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs. Switch matrix for flexible configuration of each I/O pin function. CRC engine. DMA with 18 channels and 9 trigger inputs.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Power-On Reset (POR). Brownout detect (BOD). Unique device serial number for identification. Single power supply (1.8 V to 3.6 V). Operating temperature range -40 °C to +105 °C. Available in a TSSOP20 and HVQFN33 (5x5) package. 3.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 5. Marking 20 Terminal 1 index area Terminal 1 index area 1 aaa-014766 Fig 1. TSSOP20 package marking aaa-014382 Fig 2. HVQFN33 package marking The HVQFN33 packages typically have the following top-side marking: 82xJ xx xx yywwxR The TSSOP20 packages typically have the following top-side marking: LPC82x Mx01J xxxxxxxx zzywwxR In the last line, field ‘y’ or ‘yy’ states the year the device was manufactured.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 6.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 7.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7.2 Pin description The pin description table Table 3 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable through the switch matrix between GPIO and the comparator, ADC, SWD, RESET, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Symbol HVQFN33 Pin description TSSOP20 Table 3. PIO0_4/ADC_11/ TRSTN/WAKEUP 6 4 [3] Reset state[1] Type Description I; PU IO PIO0_4 — General-purpose port 0 input/output 4. In boundary scan mode: TRST (Test Reset). In ISP mode, this pin is the U0_TXD pin. This pin triggers a wake-up from Deep power-down mode. If the part must wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Symbol HVQFN33 Pin description TSSOP20 Table 3. PIO0_14/ ACMP_I3/ADC_2 20 25 PIO0_15 11 Reset state[1] [2] I; PU Type Description IO PIO0_14 — General-purpose port 0 input/output 14. A ACMP_I3 — Analog comparator common input 3. A ADC_2 — ADC input 2. 15 [5] I; PU IO PIO0_15 — General-purpose port 0 input/output 15. I; PU IO PIO0_16 — General-purpose port 0 input/output 16.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. This pin is active in Deep power-down mode and includes a 20 ns glitch filter (active in all power modes). In Deep power-down mode, pulling the WAKEUP pin LOW wakes up the chip.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 4. LPC82x Product data sheet Movable functions (assign to pins PIO0_0 to PIO0_28 through switch matrix) Function name Type Description SPI1_MISO I/O Master In Slave Out for SPI1. SPI1_SSEL0 I/O Slave select 0 for SPI1. SPI1_SSEL1 I/O Slave select 1 for SPI1. SCT_PIN0 I Pin input 0 to the SCT input multiplexer. SCT_PIN1 I Pin input 1 to the SCT input multiplexer.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8. Functional description 8.1 ARM Cortex-M0+ core The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. The core revision is r0p1. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LPC82x 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus APB peripherals 0xE000 0000 reserved 0x4007 8000 0xA000 8000 GPIO PINT 29 I2C3 28 I2C2 27 USART2 26 USART1 25 USART0 24 reserved 23 SPI1 22 SPI0 21 I2C1 20 I2C0 19 reserved 15 reserved 14 reserved 13 reserved 12 reserved 11 input mux 10 DMA TRIGMUX 9 analog comparator 8 PMU 0x4002 0000 7 12-bit ADC 0x4001 C000 6 reserved 0x
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • • • • Tightly coupled interrupt controller provides low interrupt latency. Controls system exceptions and peripheral interrupts. Supports 32 vectored interrupts. In the LPC82x, the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation using the ARM exceptions SVCall and PendSV.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Digital input: Repeater mode enabled/disabled. • Digital input: Programmable input digital filter selectable on all pins. • Analog input: Selected through the switch matrix.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.10 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller – Pin interrupts can wake up the LPC82x from sleep mode, deep-sleep mode, and power-down mode. • Pin interrupt pattern match engine – Up to eight pins can be selected from all digital pins to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • 7, 8, or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) • Parity generation and checking: odd, even, or none. • One transmit and one receive data buffer.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master. The I2C0-bus functions are fixed-pin functions.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller – Four inputs. Each input is configurable through an input multiplexer to use one of four external pins (connected through the switch matrix) or one of four internal sources. The maximum input signal frequency is 25 MHz. – Six outputs. Connected to pins through the switch matrix. • Counter/timer features: – Each SCTimer is configurable as two 16-bit counters or one 32-bit counter.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.17 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 8.17.1 Features • 31-bit interrupt timer • Four channels independently counting down from individually set values • Bus stall, repeat and one-shot interrupt modes 8.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • The WKT can be used for waking up the part from any reduced power mode, including Deep power-down mode, or for general-purpose timing. 8.20 Analog comparator (ACMP) The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Voltage ladder source voltage is selectable from an external pin or the main 3.3 V supply voltage rail. • Voltage ladder can be separately powered down for applications only requiring the comparator function. • Interrupt output is connected to NVIC. • Comparator level output is connected to output pin ACMP_O. • One comparator output is internally collected to the ADC trigger input multiplexer. 8.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Each oscillator, except the low-frequency oscillator, can be used for more than one purpose as required in a particular application. Following reset, the LPC82x operates from the IRC until switched by software allowing the part to run without any external crystal and the bootloader code to operate at a known frequency. See Figure 9 for an overview of the LPC82x clock generation. 8.22.1.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.22.6.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. 8.23 System control 8.23.1 Reset Reset has four sources on the LPC82x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.23.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.24 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points. The Micro Trace Buffer is implemented on the LPC82x. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH).
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions [2] VDD supply voltage (core and external rail) Vref reference voltage on pin VREFP input voltage 5 V tolerant I/O pins; VDD 1.8 V VI Max Unit 0.5 +4.6 V 0.5 VDD V [3][4] 0.5 +5.5 V on I2C open-drain pins PIO0_10, PIO0_11 [5] 0.5 +5.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 10.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11. Static characteristics 11.1 General operating conditions Table 7. General operating conditions Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min fclk clock frequency internal CPU/system clock VDD supply voltage (core and external rail) Vref reference voltage Typ[1] Max Unit - - 30 MHz 1.8 3.3 3.6 V on pin VREFP 2.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.2 Supply pins Table 8. Static characteristics, supply pins Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions IDD supply current Active mode; code Min Typ[1] Max Unit - 1.85 - mA - 1.04 - mA - 3.95 - mA - 3.2 - mA - 1.35 - mA - 0.8 - mA - 2.55 - mA - 2.1 - mA 158 300 A - 400 A while(1){} executed from flash; system clock = 12 MHz; default mode; VDD = 3.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics, supply pins …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IDD supply current Deep power-down mode; VDD = 3.3 V; 10 kHz low-power oscillator and self-wake-up timer (WKT) enabled - 1.1 - A Deep power-down mode; VDD = 3.3 V; external clock input WKTCLKIN @ 10 kHz with self-wake-up timer enabled - 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.3 Electrical pin characteristics Table 9. Static characteristics, electrical pin characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins configured as digital pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10[2] nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 9. Static characteristics, electrical pin characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol VI Parameter Conditions input voltage VDD 1.8 V [4] Min Typ[1] Max Unit 0 - 5.0 V [6] VDD = 0 V 0 - 3.6 V output active 0 - VDD V HIGH-level input voltage 0.7VDD - - V VO output voltage VIH VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [5] VDD supply voltage must be present. [6] 3-state outputs go into 3-state mode in Deep power-down mode. [7] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [8] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 12. [9] To VSS. VDD IOL Ipd pin PIO0_n + A IOH Ipu pin PIO0_n - + A aaa-010819 Fig 12.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.4 Power consumption Power measurements in Active, Sleep, Deep-sleep, and Power-down modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW. aaa-013992 4 30 MHz 24 MHz 12 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz IDD (mA) 3 2 1 0 1.8 2.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-013993 4 30 MHz 24 MHz 12 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz IDD (mA) 3 2 1 0 -40 10 60 temperature (°C) 110 Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: external clock; IRC, PLL disabled.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-013994 2.5 IDD (mA) 30 MHz 24 MHz 12 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1 MHz 2 1.5 1 0.5 0 -40 10 60 temperature (°C) 110 Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: external clock; IRC, PLL disabled.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-013984 25 IDD (μA) 20 15 VDD V 3.6 VV DD == 3.6 3.3 V 1.8 V 10 5 0 -40 -10 20 50 80 temperature (°C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 17. Power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD aaa-013985 2 IDD (μA) (uA) 1.5 VDD = 3.6 V 3.3 V 2.7 V 1.8 V 1 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-013991 3 IDD (μA) 2.5 V 3.6 DD = 3.6 V 3.3 V 2.4 V 1.8 V 2 1.5 1 0.5 0 -40 -10 20 50 80 temperature (°C) 110 WKT running with internal 10 kHz low-power oscillator. Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (internal clock) aaa-014386 2 IDD (μA) VDD == 3.6 VDD 3.6 VV 3.3 V 2.7 V 1.8 V 1.5 1 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-014388 3 IDD (μA) 2.5 VDD == 3.6 VDD 3.6 VV 3.3 V 2.7 V 1.8 V 2 1.5 1 0.5 0 -40 -10 20 50 80 temperature (°C) 110 WKT running with external 32 kHz clock. Clock input waveform: square wave with rise time and fall time of 5 ns. Fig 21. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (external 32 kHz input clock) aaa-014389 25 IDD (μA) 20 VDD = 3.6 V 15 3.3 V 10 2.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.5 CoreMark data aaa-014006 2.5 coremark score ((iterations/s)/MHz) CPU performance/efficiency CPU/efficiency 2 default 1.5 low-current 1 0.5 0 0 6 12 18 24 system clock frequency (MHz) 30 Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register; BOD disabled; internal pull-up resistors enabled. Measured with Keil uVision 5.10.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.6 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG. and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code accessing the peripheral is executed. Measured on a typical sample at Tamb = 25 C.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 10. Power consumption for individual analog and digital blocks …continued Typical supply current in μA Peripheral Notes Main clock frequency = n/a 12 MHz 30 MHz - 57 141 Digital controller only. Analog portion of the ADC disabled in the PDRUNCFG register. - 57 141 Combined analog and digital logic. ADC enabled in the PDRUNCFG register and LPWRMODE bit set to 1 in the ADC CTRL register (ADC in low-power mode).
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-013964 40 IOL (mA) -40 °C C 25 °C C 90 °C C 105 °C C 30 -40 °C C 25 °C C 90 °C C 105 °C C 45 20 30 10 15 0 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD = 1.8 V; on pins PIO0_10 and PIO0_11. Fig 26. aaa-013972 60 IOL (mA) I2C-bus 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD = 3.3 V; on pins PIO0_10 and PIO0_11.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-013977 1.8 VOH (V) 1.7 -40 °C C 25 °C C 90 °C C 105 °C C aaa-013978 3.5 VOH (V) 3.2 -40 °C C 25 °C C 90 °C C 105 °C C 1.6 2.9 1.5 2.6 1.4 2.3 1.3 1.2 2 0 1.5 3 4.5 IOH (mA) 6 Conditions: VDD = 1.8 V; standard port pins. 0 8 16 IOH (mA) 24 Conditions: VDD = 3.3 V; standard port pins. Fig 28.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-013981 35 aaa-013982 80 Ipd pu (μA) (uA) Ipd (μA) (uA) 28 60 21 -40 °C C 25 °C C 90 °C C 105 °C C 14 -40 °C C 25 °C C 90 °C C 105 °C C 40 20 7 0 0 0 0.7 1.4 2.1 2.8 VI (V) 3.5 0 Conditions: VDD = 1.8 V; standard port pins. 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 30. Typical pull-down current IPD versus input voltage VI 12. Dynamic characteristics 12.1 Flash/EEPROM memory Table 11.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 12. Dynamic characteristic: external clock (XTALIN input) Tamb = 40 C to +105 C; VDD over specified ranges.[1] Typ[2] Symbol Parameter Min Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) 0.4 - - ns tCLCX clock LOW time Tcy(clk) 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller aaa-014008 12.2 f (MHz) VDDV= 3.6 V 3.6 3.3 V 3V 2.7 V 2.4 V 2.1 V 2V 1.8 V 12.1 12 11.9 11.8 -40 -10 20 50 80 temperature (°C) 110 Conditions: Frequency values are typical values. 12 MHz 1.5 % accuracy is guaranteed for 2.7 V VDD 3.6 V. Variations between parts may cause the IRC to fall outside the 12 MHz 1.5 % accuracy specification for voltages below 2.7 V. Fig 32.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.3.1 I/O pins Table 15. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +105 C; 3.0 V VDD 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 12.3.2 WKTCLKIN pin (wake-up clock input) Table 16.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 18. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C; values guaranteed by design.[2] Symbol Parameter Conditions Min Max Unit tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0.5 - s Standard-mode 4.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller WI 6'$ W68 '$7 W+' '$7 WI 6&/ W9' '$7 W+,*+ W/2: 6 I6&/ DDD Fig 33. I2C-bus pins clock timing LPC82x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.3.5 SPI interfaces In master mode, the maximum supported bit rate is limited by the maximum system clock to 30 Mbit/s. In slave mode, assuming a set-up time of 3 ns for the external device and neglecting any PCB trace delays, the maximum supported bit rate is 1/(2 x (26 ns + 3 ns)) = 17 Mbit/s at 3.0 V <= VDD <= 3.6 V and 13 Mbit/s at 1.8 V <= VDD < 3.0 V.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MOSI (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MISO (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MISO (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MISO (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MOSI (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MOSI (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.3.6 USART interface The maximum USART bit rate is 10 Mbit/s in synchronous mode master mode and 10 Mbit/s in synchronous slave mode. Remark: USART functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11. Table 20. USART dynamic characteristics Tamb = 40 C to 105 C; 1.8 V <= VDD <= 3.6 V unless noted otherwise; CL = 10 pF; input slew = 10 ns.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13. Characteristics of analog peripherals 13.1 BOD Table 21. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Min Typ Max Unit Vth threshold voltage interrupt level 1 assertion - 2.25 - V de-assertion - 2.40 - V interrupt level 2 assertion - 2.54 - V de-assertion - 2.68 - V assertion - 2.85 - V de-assertion - 2.95 - V assertion - 1.46 - V de-assertion - 1.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13.2 ADC Table 22. 12-bit ADC static characteristics Tamb = 40 C to +105 C unless noted otherwise; VDD = 2.4 V to 3.6 V; VREFP = VDD; VREFN = VSS. Symbol Parameter VIA analog input voltage Vref reference voltage Cia analog input capacitance fclk(ADC) ADC clock frequency sampling frequency fs Conditions on pin VREFP Min Typ Max Unit 0 - VDD V 2.4 - VDD V - - 0.32 pF 30 MHz 2.7 V <= VDD <= 3.6 V [2] - - 2.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller ADC R1 = 0.25 kΩ...2.5 kΩ ADCn_0 Rsw = 5 Ω...25 Ω Cio ADCn_[1:11] DAC CDAC Cio Cia aaa-011748 Fig 37. ADC input impedance LPC82x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13.3 Comparator and internal voltage reference Table 23. Internal voltage reference static and dynamic characteristics Tamb = 40 C to +105 C; VDD = 3.3 V; hysteresis disabled in the comparator CTRL register. Symbol Parameter Conditions Min Typ Max Unit VO output voltage Tamb = 25 C to 105C 860 - 940 mV Tamb = 25 C 904 mV aaa-014424 0.910 VO ref (mV) (V) 0.905 0.900 0.895 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 24. Comparator characteristics …continued Tamb = 40 C to +105 C unless noted otherwise; VDD = 1.8 V to 3.6 V. Symbol Parameter Conditions tPD propagation delay HIGH to LOW; VDD = 3.0 V; Tamb = 105 °C propagation delay tPD Vhys hysteresis voltage Min Typ Max Unit VIC = 0.1 V; 100 mV overdrive input [1][2][4] - 140 - ns VIC = 0.1 V; rail-to-rail input [1][2] - 190 - ns VIC = 1.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 26. Comparator voltage ladder reference static characteristics VDD = 1.8 V to 3.6 V. Tamb = -40 C to + 105C; external or internal reference.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14. Application information 14.1 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended to couple the input through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg).
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller /3& / ;7$/,1 ;7$/287 &/ &3 ;7$/ 56 &; &; DDD Fig 41. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 27.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller according to the increase in parasitics of the PCB layout. 14.3 Connecting power, clocks, and debug functions Figure 42 shows the basic board connections used to power the LPC82x, connect the external crystal, and provide debug capabilities via the serial wire port.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 3.3 V 3.3 V SWD connector Note 4 ~10 kΩ - 100 kΩ SWDIO/PIO0_2 1 2 3 4 5 6 n.c. 7 8 n.c. SWCLK/PIO0_3 PIO0_8/XTALIN ~10 kΩ - 100 kΩ C1 n.c. 9 10 DGND PIO0_9/XTALOUT RESET/PIO0_5 Note 1 C2 DGND VSS DGND DGND Note 2 3.3 V VDD (2 to 5 pins) VSSA LPC82x 0.1 μF 0.01 μF AGND DGND PIO0_12 ISP select pin PIO0_6/ADC_1/VDDCMP Note 5 (ADC_1), Note 3 (VDDCMP) Note 5 ADC_0 Note 3 VREFP 3.3 V 0.1 μF 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0 to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 15. Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B A terminal 1 index area A A1 E c detail X C e1 e 9 y1 C C A B C v w 1/2 e b y 16 L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 Dimensions (mm are the original dimensions) Unit(1) mm A(1) A1 b max 0.05 0.30 nom 0.85 min 0.00 0.18 c D(1) Dh E(1) Eh 5.1 3.75 5.1 3.75 0.2 4.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 16. Soldering Footprint information for reflow soldering of TSSOP20 package SOT360-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 sot360-1_fr Fig 45.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Footprint information for reflow soldering of HVQFN33 package Hx Gx see detail X P nSPx By Hy Gy SLy Ay nSPy C D SLx Bx Ax 0.60 solder land 0.30 solder paste detail X occupied area Dimensions in mm P Ax Ay Bx By C D Gx Gy Hx Hy SLx SLy nSPx nSPy 0.5 5.95 5.95 4.25 4.25 0.85 0.27 5.25 5.25 6.2 6.2 3.75 3.75 3 3 Issue date 11-11-15 11-11-20 002aag766 Fig 46.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 17. Abbreviations Table 31. Abbreviations Acronym Description AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General-Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter 18.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 19. Revision history Table 32. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC82X v.1 20141001 Product data sheet - LPC82x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 1 October 2014 - © NXP Semiconductors N.V. 2014. All rights reserved.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 22. Contents 1 2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.7 8.8 8.8.1 8.9 8.10 8.10.1 8.11 8.11.1 8.12 8.12.1 8.12.2 8.13 8.13.1 8.14 8.14.1 8.15 8.15.1 8.16 8.16.1 8.16.2 8.17 8.17.1 8.18 8.18.1 8.19 8.19.1 8.20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LPC82x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13.1 13.2 13.3 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparator and internal voltage reference . . Application information. . . . . . . . . . . . . . . . . . XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . .
