Datasheet

LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 97 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
11.4 Internal oscillators
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
11.5 I/O pins
[1] Applies to standard port pin. For details, see the LPC408x/7x IBIS model available on the NXP website.
11.6 SSP interface
[1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited
by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster
than that. At and below the maximum frequency, T
cy(clk)
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
main
.
The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the main clock frequency f
main
, the
SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register),
and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
Table 20. Dynamic characteristic: internal oscillators
T
amb
=  40  C to +85  C; 2.7 V  V
DD(3V3)
 3.6 V.
[1]
Symbol Parameter Min Typ
[2]
Max Unit
f
osc(RC)
internal RC oscillator frequency 11.88 12 12.12 MHz
f
i(RTC)
RTC input frequency - 32.768 - kHz
Table 21. Dynamic characteristic: I/O pins
[1]
T
amb
=  40  C to +85  C; V
DD(3V3)
over specified ranges.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time pin configured as
output
3.0 - 5.0 ns
t
f
fall time pin configured as
output
2.5 - 5.0 ns
Table 22. Dynamic characteristics: SSP pins in SPI mode
C
L
=10pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
SSP master
T
cy(clk)
clock cycle time full-duplex
mode
[1]
30 - ns
when only
transmitting
30 - ns
t
DS
data set-up time in SPI mode
[2]
14.8 - ns
t
DH
data hold time in SPI mode
[2]
2- ns
t
v(Q)
data output valid time in SPI mode
[2]
-6.3ns
t
h(Q)
data output hold time in SPI mode
[2]
2.4 - ns
SSP slave
T
cy(clk)
clock cycle time
[3]
100 - ns
t
DS
data set-up time in SPI mode
[3][4]
14.8 - ns
t
DH
data hold time in SPI mode
[3][4]
2- ns
t
v(Q)
data output valid time in SPI mode
[3][4]
-6.3ns
t
h(Q)
data output hold time in SPI mode
[3][4]
2.4 - ns