Datasheet

LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 96 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0. See the LPC408x/7x user
manual for details.
11.3 External clock
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
Table 18. Dynamic characteristics: Dynamic external memory interface programmable
clock delays
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V.Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
t
d
delay time Programmable delay block 0 (CMDDLY
or CLKOUTnDLY bit 0 = 1)
[1]
0.1 0.2 ns
Programmable delay block 1 (CMDDLY
or CLKOUTnDLY bit 1 = 1)
[1]
0.2 0.5 ns
Programmable delay block 2 (CMDDLY
or CLKOUTnDLY bit 2 = 1)
[1]
0.5 1.3 ns
Programmable delay block 3 (CMDDLY
or CLKOUTnDLY bit 3 = 1)
[1]
1.2 2.9 ns
Programmable delay block 4 (CMDDLY
or CLKOUTnDLY bit 4 = 1)
[1]
2.4 6.0 ns
Table 19. Dynamic characteristic: external clock (see Figure 40)
T
amb
=  40  C to +85  C; V
DD(3V3)
over specified ranges.
[1]
Symbol Parameter Min Typ
[2]
Max Unit
f
osc
oscillator frequency 1 - 25 MHz
T
cy(clk)
clock cycle time 40 - 1000 ns
t
CHCX
clock HIGH time T
cy(clk)
 0.4 - - ns
t
CLCX
clock LOW time T
cy(clk)
 0.4 - - ns
t
CLCH
clock rise time - - 5 ns
t
CHCL
clock fall time - - 5 ns
Fig 23. External clock timing (with an amplitude of at least V
i(RMS)
= 200 mV)
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
002aaa907