Datasheet

LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 95 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[1] Refers to SDRAM clock signal EMC_CLKx.
[2] The data input set-up time has to be selected with the following margin:
t
su(D)
+ delay time of feedback clock  SDRAM access time  board delay time  0.
[3] The data input hold time has to be selected with the following margin:
t
h(D)
+ SDRAM access time - board delay time - delay time of feedback clock  0.
Write cycle parameters
t
d(QV)
data output valid delay time (CMDDLY + 1) 
0.25 + 5.9
(CMDDLY + 1) 
0.25 + 8.7
(CMDDLY + 1) 
0.25 + 13.1
ns
t
h(Q)
data output hold time (CMDDLY + 1) 
0.25 + 1.0
(CMDDLY + 1) 
0.25 + 2.0
(CMDDLY + 1) 
0.25 + 3.9
ns
Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
…continued
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Min Typ Max Unit
Fig 22. Dynamic external memory interface signal timing
002aah129
T
cy(clk)
EMC_CLKn
delay = 0
EMC_DYCSn,
EMC_RAS,
EMC_CAS,
EMC_WE,
EMC_CKEOUTn,
EMC_A[22:0],
EMC_DQMOUTn
t
h(Q)
t
h(D)
t
su(D)
EMC_D[31:0]
write
EMC_D[31:0]
read
t
d(QV)
t
h(x)
t
d(xV)