Datasheet

LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 94 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[1] Refers to SDRAM clock signal EMC_CLKx.
[2] CLKDLY = CLKOUTnDLY, where n = 0, 1.
[3] The data input set-up time has to be selected with the following margin:
t
su(D)
+ delay time of feedback clock  SDRAM access time  board delay time  0.
[4] The data input hold time has to be selected with the following margin:
t
h(D)
+ SDRAM access time  board delay time  delay time of feedback clock  0.
Write cycle parameters
t
d(QV)
data output valid delay time
[2]
(CLKDLY + 1) 
0.25 + 3.9
(CLKDLY + 1) 
0.25 + 5.4
(CLKDLY + 1) 
0.25 + 7.8
ns
t
h(Q)
data output hold time
[2]
(CLKDLY + 1) 
0.25  1.1
(CLKDLY + 1) 
0.25  1.2
(CLKDLY + 1) 
0.25  1.4
ns
Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00
…continued
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Min Typ Max Unit
Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Min Typ Max Unit
Common to read and write cycles
T
cy(clk)
clock cycle time
[1]
12.5 - - ns
t
d(SV)
chip select valid delay time (CMDDLY + 1) 
0.25 + 4.9
(CMDDLY + 1) 
0.25 + 6.7
(CMDDLY + 1) 
0.25 + 10.4
ns
t
h(S)
chip select hold time (CMDDLY + 1) 
0.25 + 1.2
(CMDDLY + 1) 
0.25 + 2.1
(CMDDLY + 1) 
0.25 + 3.8
ns
t
d(RASV)
row address strobe valid delay time (CMDDLY + 1) 
0.25 + 4.9
(CMDDLY + 1) 
0.25 + 6.8
(CMDDLY + 1) 
0.25 + 10.4
ns
t
h(RAS)
row address strobe hold time (CMDDLY + 1) 
0.25 + 1.3
(CMDDLY + 1) 
0.25 + 2.3
(CMDDLY + 1) 
0.25 + 4.3
ns
t
d(CASV)
column address strobe valid delay
time
(CMDDLY + 1) 
0.25 + 4.8
(CMDDLY + 1) 
0.25 + 6.7
(CMDDLY + 1) 
0.25 + 10.2
ns
t
h(CAS)
column address strobe hold time (CMDDLY + 1) 
0.25 + 1.2
(CMDDLY + 1) 
0.25 + 2.2
(CMDDLY + 1) 
0.25 + 4.1
ns
t
d(WV)
write valid delay time (CMDDLY + 1) 
0.25 + 5.1
(CMDDLY + 1) 
0.25 + 7.1
(CMDDLY + 1) 
0.25 + 10.9
ns
t
h(W)
write hold time (CMDDLY + 1) 
0.25 + 1.5
(CMDDLY + 1) 
0.25 + 2.6
(CMDDLY + 1) 
0.25 + 4.8
ns
t
d(AV)
address valid delay time (CMDDLY + 1) 
0.25 + 5.5
(CMDDLY + 1) 
0.25 + 7.7
(CMDDLY + 1) 
0.25 + 11.9
ns
t
h(A)
address hold time (CMDDLY + 1) 
0.25 + 1.0
(CMDDLY + 1) 
0.25 + 1.8
(CMDDLY + 1) 
0.25 + 3.5
ns
Read cycle parameters
t
su(D)
data input set-up time
[2]
(FBCLKDLY + 1)
 0.25 + 4.1
(FBCLKDLY + 1)
 0.25 + 2.3
(FBCLKDLY + 1)
 0.25  0.9
ns
t
h(D)
data input hold time
[3]
(FBCLKDLY + 1)
 0.25 + 4.0
(FBCLKDLY + 1)
 0.25 + 4.7
(FBCLKDLY + 1)
 0.25 + 5.8
ns