Datasheet
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 93 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 21. External static memory burst read cycle
RD
5
RD
5
RD
5
RD
5
EMC_Ax
EMC_CSx
EMC_OE
EMC_BLSx
EMC_WE
EMC_Dx
002aag216
Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00
C
L
=30pF, T
amb
=
40
C to 85
C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Min Typ Max Unit
Common to read and write cycles
T
cy(clk)
clock cycle time
[1]
12.5--ns
t
d(SV)
chip select valid delay time
[2]
(CLKDLY + 1)
0.25 + 2.8
(CLKDLY + 1)
0.25 + 3.5
(CLKDLY + 1)
0.25 + 5.1
ns
t
h(S)
chip select hold time
[2]
(CLKDLY + 1)
0.25 1.0
(CLKDLY + 1)
0.25 1.1
(CLKDLY + 1)
0.25 1.5
ns
t
d(RASV)
row address strobe valid delay time
[2]
(CLKDLY + 1)
0.25 + 2.8
(CLKDLY + 1)
0.25 + 3.6
(CLKDLY + 1)
0.25 + 5.1
ns
t
h(RAS)
row address strobe hold time
[2]
(CLKDLY + 1)
0.25 0.8
(CLKDLY + 1)
0.25 0.9
(CLKDLY + 1)
0.25 1.0
ns
t
d(CASV)
column address strobe valid delay time
[2]
(CLKDLY + 1)
0.25 + 2.7
(CLKDLY + 1)
0.25 + 3.4
(CLKDLY + 1)
0.25 + 4.9
ns
t
h(CAS)
column address strobe hold time
[2]
(CLKDLY + 1)
0.25 0.8
(CLKDLY + 1)
0.25 1.0
(CLKDLY + 1)
0.25 1.2
ns
t
d(WV)
write valid delay time
[2]
(CLKDLY + 1)
0.25 + 3.2
(CLKDLY + 1)
0.25 + 4.1
(CLKDLY + 1)
0.25 + 6.0
ns
t
h(W)
write hold time
[2]
(CLKDLY + 1)
0.25 0.6
(CLKDLY + 1)
0.25 0.67
(CLKDLY + 1)
0.25 0.7
ns
t
d(AV)
address valid delay time
[2]
(CLKDLY + 1)
0.25 + 3.4
(CLKDLY + 1)
0.25 + 4.6
(CLKDLY + 1)
0.25 + 6.8
ns
t
h(A)
address hold time
[2]
(CLKDLY + 1)
0.25 1.1
(CLKDLY + 1)
0.25 1.4
(CLKDLY + 1)
0.25 1.8
ns
Read cycle parameters
t
su(D)
data input set-up time
[3]
(FBCLKDLY +
1) 0.25 - 0.9
(FBCLKDLY +
1) 0.25 + 2.3
-ns
t
h(D)
data input hold time
[4]
(FBCLKDLY +
1) 0.25 + 4.0
(FBCLKDLY +
1) 0.25 + 4.7
(FBCLKDLY +
1) 0.25 + 5.8
ns