Datasheet

LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 91 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[1] Parameters are shown as RD
n
or WD
n
in Figure 19 as indicated in the Conditions column.
t
am
memory access
time
RD
5
[4]
[3]
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 9.6
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 13.2
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 20.2
ns
t
h(D)
data input hold time RD
6
[5]
[3]
5.0 7.2  ns
t
CSHBLSH
CS HIGH to BLS
HIGH time
PB = 1 2.7 3.4 4.9 ns
t
CSHOEH
CS HIGH to OE
HIGH time
[3]
2.4 3.1 4.2 ns
t
OEHANV
OE HIGH to address
invalid time
[3]
0.77 1.2 1.86 ns
t
deact
deactivation time RD
7
[3]
- 4.3 6.1 ns
Write cycle parameters
[2]
t
CSLAV
CS LOW to address
valid time
WR
1
3.3 4.3 6.1 ns
t
CSLDV
CS LOW to data
valid time
WR
2
3.4 4.8 6.6 ns
t
CSLWEL
CS LOW to WE
LOW time
WR
3
; PB =1
[3]
2.6 + T
cy(clk)

(1 + WAITWEN)
3.3 + T
cy(clk)

(1 + WAITWEN)
4.6 + T
cy(clk)

(1 + WAITWEN)
ns
t
CSLBLSL
CS LOW to BLS
LOW time
WR
4
; PB = 1
[3]
2.7 3.5 4.9 ns
t
WELWEH
WE LOW to WE
HIGH time
WR
5
; PB =1
[3]
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
 2.3
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
 2.8
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
 3.8
ns
t
BLSLBLSH
BLS LOW to BLS
HIGH time
PB = 1
[3]
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 2.8
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 3.5
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 5.0
ns
t
WEHDNV
WE HIGH to data
invalid time
WR
6
; PB =1
[3]
3.1 + T
cy(clk)
4.3 + T
cy(clk)
5.8 + T
cy(clk)
ns
t
WEHEOW
WE HIGH to end of
write time
WR
7
; PB = 1
[6][3]
T
cy(clk)
 2.6 T
cy(clk)
 3.4 T
cy(clk)
 4.6 ns
t
BLSHDNV
BLS HIGH to data
invalid time
PB = 1 3.4 4.8 6.6 ns
t
WEHANV
WE HIGH to
address invalid time
PB = 1
[3]
3.0 + T
cy(clk)
3.8 + T
cy(clk)
5.3 + T
cy(clk)
ns
t
deact
deactivation time WR
8
; PB = 0; PB =
1
[3]
3.3 4.3 6.1 ns
t
CSLBLSL
CS LOW to BLS
LOW
WR
9
; PB = 0
[3]
2.7 + T
cy(clk)

(1 + WAITWEN)
3.5 + T
cy(clk)

(1 + WAITWEN)
4.9 + T
cy(clk)

(1 + WAITWEN)
ns
t
BLSLBLSH
BLS LOW to BLS
HIGH time
WR
10
; PB = 0
[3]
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 2.8
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
3.5
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 5.0
ns
t
BLSHEOW
BLS HIGH to end of
write time
WR
11
; PB = 0
[6][3]
3.3 + T
cy(clk)
4.4 + T
cy(clk)
6.1 + T
cy(clk)
ns
t
BLSHDNV
BLS HIGH to data
invalid time
WR
12
; PB = 0
[3]
3.4 + T
cy(clk)
4.8 + T
cy(clk)
6.6 + T
cy(clk)
ns
Table 15. Dynamic characteristics: Static external memory interface
…continued
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter
[1]
Conditions
[1]
Min Typ Max Unit