Datasheet

Product data sheet Rev. 3.1 — 1 September 2014 64 of 138

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto-baud capability.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing.

• All UARTs have DMA support for both transmit and receive.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

• USART4 includes an IrDA mode to support infrared communication.

• USART4 supports synchronous mode and a smart card mode conforming to

ISO7816-3.

7.23 SPIFI

The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM

Cortex-M4 processor with little performance penalty compared to parallel flash devices

with higher pin count.

The entire flash content is accessible as normal memory using byte, halfword, and word

accesses by the processor and/or DMA channels.

SPIFI provides sufficient flexibility to be compatible with common flash devices and

includes extensions to help insure compatibility with future devices.

7.23.1 Features

• Quad SPI Flash Interface (SPIFI) interface to external flash.

• Transfer rates of up to SPIFI_CLK/2 bytes per second.

• Code in the serial flash memory can be executed as if it was in the CPU’s internal

memory space. This is accomplished by mapping the external flash memory directly

into the CPU memory space.

• Supports 1-, 2-, and 4-bit bidirectional serial protocols.

• Half-duplex protocol compatible with various vendors and devices.

• Supported by a driver library available from NXP Semiconductors.

7.24 SSP serial I/O controller

The LPC408x/7x contain three SSP controllers. The SSP controller is capable of

operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data flowing from the master to the slave and from the slave to the master. In

practice, often only one of these data flows carries meaningful data.