Datasheet

LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 52 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
7.5 EEPROM
The LPC408x/7x contains up to 4032 byte of on-chip byte-erasable and
byte-programmable EEPROM data memory.
7.6 On-chip SRAM
The LPC408x/7x contain a total of up to 96 kB on-chip SRAM data memory. This includes
64 kB main SRAM, accessible by the CPU and DMA controller on a higher-speed bus,
and up to two additional 16 kB peripheral SRAM blocks situated on a separate slave port
on the AHB multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.
7.7 Memory Protection Unit (MPU)
The LPC408x/7x have a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
7.8 Memory map
Table 4. LPC408x/7x memory usage and details
Address range General Use Address range details and description
0x0000 0000 to
0x1FFF FFFF
On-chip non-volatile
memory
0x0000 0000 to 0x0007 FFFF For devices with 512 kB of flash memory.
0x0000 0000 to 0x0003 FFFF For devices with 256 kB of flash memory.
0x0000 0000 to 0x0001 FFFF For devices with 128 kB of flash memory.
0x0000 0000 to 0x0000 FFFF For devices with 64 kB of flash memory.
On-chip SRAM 0x1000 0000 to 0x1000 FFFF For devices with 64 kB of main SRAM.
0x1000 0000 to 0x1000 7FFF For devices with 32 kB of main SRAM.
0x1000 0000 to 0x1000 3FFF For devices with 16 kB of main SRAM.
Boot ROM 0x1FFF 0000 to 0x1FFF 1FFF 8 kB Boot ROM with flash services.
0x2000 0000 to
0x3FFF FFFF
On-chip SRAM
(typically used for
peripheral data)
0x2000 0000 to 0x2000 1FFF Peripheral SRAM - bank 0 (first 8 kB)
0x2000 2000 to 0x2000 3FFF Peripheral SRAM - bank 0 (second 8 kB)
0x2000 4000 to 0x2000 7FFF Peripheral SRAM - bank 1 (16 kB)
AHB peripherals 0x2008 0000 to 0x200B FFFF See Figure 9
for details
0x4000 0000 to
0x7FFF FFFF
APB Peripherals 0x4000 0000 to 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x4008 0000 to 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of
16 kB each.