Datasheet

Product data sheet Rev. 3.1 — 1 September 2014 51 of 138

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

[9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0

(Full-speed and Low-speed mode only).

[10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[11] Open-drain 5 V tolerant digital I/O pad, compatible with I

C-bus 1 MHz specification. It requires an external pull-up to provide output

functionality. When power is switched off, this pin connected to the I

C-bus is floating and does not disturb the I

C lines. Open-drain

configuration applies to all functions on this pin.

[12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[13] This pad can be powered from VBAT.

[14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be

used to drive the RTCX1 pin.

[15] If the RTC is not used, these pins can be left floating.

[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

7. Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses are faster than the system bus and

are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for

instruction fetch (I-code) and one bus for data access (D-code). The use of two core

buses allows for simultaneous operations if concurrent operations target different devices.

The LPC408x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and

other bus masters to peripherals in a flexible manner that optimizes performance by

allowing peripherals that are on different slaves ports of the matrix to be accessed

simultaneously by different bus masters.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 processor is running at frequencies of up to 120 MHz. The processor

executes the Thumb-2 instruction set for optimal performance and code size, including

hardware division, single-cycle multiply, and bit-field manipulation. A Memory Protection

Unit (MPU) supporting eight regions is included.

7.3 ARM Cortex-M4 Floating Point Unit (FPU)

Remark: The FPU is available on parts LP4088/78/76.

The FPU supports single-precision floating-point computation functionality in compliance

with the ANSI/IEEE Standard 754-2008. The FPU provides add, subtract, multiply, divide,

multiply and accumulate, and square root operations. It also performs a variety of

conversions between fixed-point, floating-point, and integer data formats.

7.4 On-chip flash program memory

The LPC408x/7x contain up to 512 kB of on-chip flash program memory. A new two-port

flash accelerator maximizes performance for use with the two fast AHB-Lite buses.