Datasheet

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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3.1 — 1 September 2014 50 of 138 NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[1] PU = internal pull-up enabled (for V
DD(REG)(3V3)
= 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground
or power to minimize power consumption.
[2] I = Input; O = Output; G = Ground; S = Supply.
[3] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[4] 5 V tolerant standard pad (5 V tolerant if V
DD(3V3)
present; if V
DD(3V3)
not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. This pad can
be powered by VBAT.
[5] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the pad is disabled.
[6] 5 V tolerant fast pad (5 V tolerant if V
DD(3V3)
present; if V
DD(3V3)
not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis.
[7] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled.
[8] Open-drain 5 V tolerant digital I/O pad, compatible with I
2
C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this
pin connected to the I
2
C-bus is floating and does not disturb the I
2
C lines. Open-drain configuration applies to all functions on this pin.
V
SS
33,
63,
77,
93,
114,
133,
148,
169,
189,
200
L3, T5,
R9,
P12,
N16,
H14,
E15,
A12,
B6, A2
H4,
P4,
L9,
L13,
G13,
D13,
C11,
B4
44,
65,
79,
103,
117,
139
31, 55,
72, 97
24, 43,
57, 78
H4,
G8,
G9,
B3
G Ground: 0 V reference for digital IO pins.
V
SSREG
32,
84,
172
D12,
K4,
P10
H3,
L8,
A10
22,
59,
119
15, 41,
83
33, 66 J7, F3 G Ground: 0 V reference for internal logic.
V
SSA
22 J2 F3 15 11 9 E2 G Analog ground: 0 V power supply and reference for the
ADC and DAC. This should be the same voltage as V
SS
,
but should be isolated to minimize noise and error.
XTAL1 44M4L2312219J1
[14]
[16]
I Input to the oscillator circuit and internal clock generator
circuits.
XTAL2 46 N4 K4 33 23 20 K1
[14]
[16]
O Output from the oscillator amplifier.
DNC - - - - - 12 - Do not connect.
Table 3. Pin description
…continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state
[1]
Type
[2]
Description