Datasheet

LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3.1 — 1 September 2014 133 of 138
NXP Semiconductors
LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
18. Revision history
Table 37. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC408X_7X v.3.1 20140901 Product data sheet CIN 201404014I LPC408X_7X v.3
Modifications:
SPIFI timing diagram corrected and specified for mode 0. See Table 27.
Added values for power consumption on SPIFI. See Table 12.
Parameter t
su(D)
updated in Table 16 “Dynamic characteristics: Dynamic external memory
interface, read strategy bits (RD bits) = 00: Minimum value changed to (FBCLKDLY + 1)
0.25 - 0.9. Maximum value removed.
ADC conversion rate in burst mode added to Table 28 “12-bit ADC characteristics.
Removed max value from parameter t
h(D)
in Table 15.
Removed min value from parameter t
deact
in Table 15.
LPC408X_7X v.3 20140501 Product data sheet CIN 201404014I LPC408X_7X v.2
Modifications:
Added TFBGA80 to features list.
Added Section 11.11 “SPIFI”.
Table 3:
Added function SSP2_SCK to pin P5[2].
Added function SSP2_SSEL to pin P5[3].
Updated pin description of STCLK.
5 ns glitch filter changed to 10 ns for EINTx pins.
LQFP80 pin 12 changed from P2[30] to DNC.
Table 11: Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC
and DAC are not used.”.
Table 28: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC
and DAC are not used.”.
Section 7.37.2 “Brownout detection”: Updated BOD interrupt and reset values.
Table 15: Added typical specs.
Table 16:
Added typical specs
Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
Table 17:
Added typical specs
Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
Table note 9 added in Table 28 “12-bit ADC characteristics”.
LPC408X_7X v.2 20130703 Product data sheet - LPC408X_7X v.1.1