Microcontrollers User manual

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 8 of 792
NXP Semiconductors
UM10237
Chapter 1: LPC24XX Introductory information
5.5 LPC2478 ordering options
6. Architectural overview
The LPC2400 microcontroller consists of an ARM7TDMI-S CPU with emulation support,
the ARM7 local bus for closely coupled, high speed access to the majority of on-chip
memory, the AMBA AHB interfacing to high speed on-chip peripherals and external
memory, and the AMBA APB for connection to other on-chip peripheral functions. The
microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte
order.
The LPC2400 implements two AHB buses in order to allow the Ethernet block to operate
without interference caused by other system activity. The primary AHB, referred to as
AHB1, includes the VIC, GPDMA controller, and EMC.
Table 10. LPC2470 ordering options
Type number Flash
(kB)
SRAM (kB) External
bus
Ethernet USB
OTG/
OHC/
Device
+ 4 kB
FIFO
CAN channels
SD/
MMC
GP
DMA
ADC channels DAC channels
Temp
range
Local bus Ethernet buffer GP/USB RTC Total
LPC2470FBD208 N/A 64 16 16 2 98 Full
32-bit
MII/RMII yes 2 yes yes 8 1 −40 °C
to
+85 °C
LPC2470FET208 N/A 64 16 16 2 98 Full
32-bit
MII/RMII yes 2 yes yes 8 1 −40 °C
to
+85 °C
Table 11. LPC2478 ordering information
Type number Package
Name Description Version
LPC2478FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm SOT459-1
LPC2478FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 ×
0.7 mm
SOT950-1
Table 12. LPC2478 ordering options
Type number Flash
(kB)
SRAM (kB) External
bus
Ethernet USB
OTG/
OHC/
Device
+ 4 kB
FIFO
CAN channels
SD/
MMC
GP
DMA
ADC channels DAC channels
Temp
range
Local bus Ethernet buffer GP/USB RTC Total
LPC2478FBD208 512 64 16 16 2 98 Full
32-bit
MII/RMII yes 2 yes yes 8 1 −40 °C
to
+85 °C
LPC2478FET208 512 64 16 16 2 98 Full
32-bit
MII/RMII yes 2 yes yes 8 1 −40 °C
to
+85 °C