Microcontrollers User manual

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 653 of 792
NXP Semiconductors
UM10237
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
6.2.6 Alarm Mask Register (AMR - 0xE002 4010)
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table 26–573
shows the relationship between the bits in the AMR and the alarms. For the
alarm function, every non-masked alarm register must match the corresponding time
counter for an interrupt to be generated. The interrupt is generated only when the counter
comparison first changes from no match to match. The interrupt is removed when a one is
written to the appropriate bit of the Interrupt Location Register (ILR). If all mask bits are
set, then the alarm is disabled.
Table 572. Counter Increment Select Mask register (CISS - address 0xE002 4040) bit description
Bit Symbol Value Description Reset
value
2:0 SubSecSel SubSecSelSub-Second Select. This field selects a count for the sub-second interrupt as
follows:
NC
000 An interrupt is generated on every 16 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 488 microseconds.
001 An interrupt is generated on every 32 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 977 microseconds.
010 An interrupt is generated on every 64 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 1.95 milliseconds.
011 An interrupt is generated on every 128 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 3.9 milliseconds.
100 An interrupt is generated on every 256 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 7.8 milliseconds.
101 An interrupt is generated on every 512 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 15.6 milliseconds.
110 An interrupt is generated on every 1024 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 31.25 milliseconds.
111 An interrupt is generated on every 2048 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 62.5 milliseconds.
6:3 Unused Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
7 SubSecEna Subsecond interrupt enable. NC
0 The sub-second interrupt is disabled.
1 The sub-second interrupt is enabled.
Table 573. Alarm Mask Register (AMR - address 0xE002 4010) bit description
Bit Symbol Description Reset
value
0 AMRSEC When 1, the Second value is not compared for the alarm. NA
1 AMRMIN When 1, the Minutes value is not compared for the alarm. NA
2 AMRHOUR When 1, the Hour value is not compared for the alarm. NA
3 AMRDOM When 1, the Day of Month value is not compared for the alarm. NA
4 AMRDOW When 1, the Day of Week value is not compared for the alarm. NA
5 AMRDOY When 1, the Day of Year value is not compared for the alarm. NA
6 AMRMON When 1, the Month value is not compared for the alarm. NA
7 AMRYEAR When 1, the Year value is not compared for the alarm. NA