Microcontrollers User manual

User manual Rev. 02 — 19 December 2008 194 of 792

NXP Semiconductors

UM10237

Chapter 10: LPC24XX General Purpose Input/Output (GPIO)

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy registers

appearing at the original addresses on the APB bus.

3.2 Interrupt generating digital ports

• PORT0 and PORT2 provide an interrupt for each port pin.

• Each port pin can be programmed to generate an interrupt on a rising edge, a falling

edge, or both.

• Edge detection is asynchronous, so it may operate when clocks are not present, such

as during Power-down mode. With this feature, level triggered interrupts are not

needed.

• Each enabled interrupt contributes to a Wakeup signal that can be used to bring the

part out of Power Down mode.

• Registers provide a software view of pending rising edge interrupts, pending falling

edge interrupts, and overall pending GPIO interrupts.

• GPIO0 and GPIO2 interrupts share the same VIC slot with the External Interrupt 3

event.

4. Applications

• General purpose I/O

• Driving LEDs or other indicators

• Controlling off-chip devices

• Sensing digital inputs, detecting edges

• Bringing the part out of Power Down mode