Datasheet
LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7.1 — 16 October 2013 17 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,
digital section of the pad is disabled.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I
2
C-bus 400 kHz specification. This pad requires an external pull-up to provide
output functionality. When power is switched off, this pin connected to the I
2
C-bus is floating and does not disturb the I
2
C lines.
Open-drain configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions (LPC2364/66/68 only). It is designed in accordance with the USB specification, revision 2.0
(Full-speed and Low-speed mode only).
[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7] This pin has no built-in pull-up and no built-in pull-down resistor.
[8] This pin has a built-in pull-up resistor.
[9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[10] Pad provides special analog functionality.
[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
RSTOUT 14 - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates
LPC2364/65/66/67/68 being in Reset state.
Note: This pin is available in LPC2364FBD100, LPC2365FBD100,
LPC2366FBD100, LPC2367FBD100, and LPC2368FBD100 devices only
(LQFP100 package).
RESET
17
[9]
F3
[9]
I External reset input: A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 22
[10][11]
H2
[10][11]
I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 23
[10][11]
G3
[10][11]
O Output from the oscillator amplifier.
RTCX1 16
[10][12]
F2
[10][12]
I Input to the RTC oscillator circuit.
RTCX2 18
[10]
G1
[10]
O Output from the RTC oscillator circuit.
V
SS
15, 31,
41, 55,
72, 97,
83
[13]
B3, B7,
C9, F1,
G7, J6,
K3
[13]
I ground: 0 V reference.
V
SSA
11
[14]
E1
[14]
I analog ground: 0 V reference. This should nominally be the same voltage
as V
SS
, but should be isolated to minimize noise and error.
V
DD(3V3)
28, 54,
71,
96
[15]
A3, C10,
H9,
K2
[15]
I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.
V
DD(DCDC)(3V3)
13, 42,
84
[16]
A7, E4,
H6
[16]
I 3.3 V DC-to-DC converter supply voltage: This is the supply voltage for
the on-chip DC-to-DC converter only.
V
DDA
10
[17]
E2
[17]
I analog 3.3 V pad supply voltage: This should be nominally the same
voltage as V
DD(3V3)
but should be isolated to minimize noise and error. This
voltage is used to power the ADC and DAC.
VREF 12
[17]
E3
[17]
I ADC reference: This should be nominally the same voltage as V
DD(3V3)
but
should be isolated to minimize noise and error. Level on this pin is used as
a reference for ADC and DAC.
VBAT 19
[17]
G2
[17]
I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC
peripheral.
Table 4. Pin description
…continued
Symbol Pin Ball Type Description