Datasheet

LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7.1 — 16 October 2013 16 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
P2[12]/EINT2/
MCIDAT2/
I2STX_WS
51
[6]
K10
[6]
I/O P2[12] — General purpose digital input/output pin.
I EINT2
— External interrupt 2 input.
O MCIDAT2 — Data line for SD/MMC interface. (LPC2367/68 only)
I/O I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
2
S-bus
specification.
P2[13]/EINT3
/
MCIDAT3/
I2STX_SDA
50
[6]
J9
[6]
I/O P2[13] — General purpose digital input/output pin.
I EINT3
— External interrupt 3 input.
O MCIDAT3 — Data line for SD/MMC interface. (LPC2367/68 only)
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I
2
S-bus specification.
P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each
bit. The operation of Port 3 pins depends upon the pin function selected via
the pin connect block. Pins 0 through 24, and 27 through 31 of this port are
not available.
P3[25]/MAT0[0]/
PWM1[2]
27
[1]
H3
[1]
I/O P3[25] — General purpose digital input/output pin.
O MAT0[0] — Match output for Timer 0, channel 0.
O PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26]/MAT0[1]/
PWM1[3]
26
[1]
K1
[1]
I/O P3[26] — General purpose digital input/output pin.
O MAT0[1] — Match output for Timer 0, channel 1.
O PWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each
bit. The operation of Port 4 pins depends upon the pin function selected via
the pin connect block. Pins 0 through 27, 30, and 31 of this port are not
available.
P4[28]/MAT2[0]/
TXD3
82
[1]
C7
[1]
I/O P4[28] — General purpose digital input/output pin.
O MAT2[0] — Match output for Timer 2, channel 0.
O TXD3 — Transmitter output for UART3.
P4[29]/MAT2[1]/
RXD3
85
[1]
E6
[1]
I/O P4[29] — General purpose digital input/output pin.
O MAT2[1] — Match output for Timer 2, channel 1.
I RXD3 — Receiver input for UART3.
DBGEN - D4
[1][8]
I DBGEN — JTAG interface control signal. Also used for boundary scanning.
Note: This pin is available in LPC2364FET100 and LPC2368FET100
devices only (TFBGA package).
TDO 1
[1][7]
A1
[1][7]
O TDO — Test Data out for JTAG interface.
TDI 2
[1][8]
C3
[1][8]
I TDI — Test Data in for JTAG interface.
TMS 3
[1][8]
B1
[1][8]
I TMS — Test Mode Select for JTAG interface.
TRST
4
[1][8]
C2
[1][8]
I TRST — Test Reset for JTAG interface.
TCK 5
[1][7]
C1
[1][7]
I TCK — Test Clock for JTAG interface. This clock must be slower than
1
⁄
6
of
the CPU clock (CCLK) for the JTAG interface to operate
RTCK 100
[1][8]
B2
[1][8]
I/O RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET
is LOW enables ETM pins (P2[9:0]) to
operate as trace port after reset.
Table 4. Pin description …continued
Symbol Pin Ball Type Description