Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16/32-Bit 72 MHz I/O number 70

1. General description

The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S

CPU with real-time emulation that combines the microcontroller with up to 512 kB of

embedded high-speed flash memory. A 128-bit wide memory interface and a unique

accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical performance in interrupt service routines and DSP algorithms, this increases

performance up to 30 % over Thumb mode. For critical code size applications, the

alternative 16-bit Thumb mode reduces code by more than 30 % with minimal

performance penalty.

The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications.

They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed

device with 4 kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels

(LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three

C-bus interfaces, and an I

S-bus interface. This blend of serial communications

interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of up to 32 kB, 16 kB

SRAM for Ethernet, 8 kB SRAM for USB and general purpose use, together with 2 kB

battery powered SRAM make these devices very well suited for communication gateways

and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one

PWM unit, a CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up

to 12 edge or level sensitive external interrupt pins make these microcontrollers

particularly suitable for industrial control and medical systems.

2. Features and benefits

 ARM7TDMI-S processor, running at up to 72 MHz

 Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on the ARM

local bus for high performance CPU access.

 8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access.

 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

 8 kB SRAM for general purpose DMA use also accessible by the USB.

 Dual Advanced High-performance Bus (AHB) system that provides for simultaneous

Ethernet DMA, USB DMA, and program execution from on-chip flash with no

contention between those functions. A bus bridge allows the Ethernet DMA to access

the other AHB subsystem.

 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

 General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP

serial interfaces, the I

S port, and the Secure Digital/MultiMediaCard (SD/MMC) card

port, as well as for memory-to-memory transfers.

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash

with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC

Rev. 7.1 — 16 October 2013 Product data sheet

Summary of content (69 pages)

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LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC Rev. 7.1 — 16 October 2013 Product data sheet 1. General description The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 512 kB of embedded high-speed flash memory.
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NXP Semiconductors LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers  Serial interfaces:  Ethernet MAC with associated DMA controller. These functions reside on an independent AHB.  USB 2.0 full-speed device with on-chip PHY and associated DMA controller (LPC2364/66/68 only).  Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO.  CAN controller with two channels (LPC2364/66/68 only).  SPI controller.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers  On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.  Boundary scan for simplified board testing is available in LPC2364FET100 and LPC2368FET100 (TFBGA package).  Versatile pin function selections allow more possibilities for using on-chip peripheral functions. 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 5.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6. Pinning information 76 100 6.1 Pinning 1 75 LPC2364FBD100 LPC2365FBD100 LPC2366FBD100 LPC2367FBD100 LPC2368FBD100 Fig 2. 50 51 26 25 002aac576 LPC2364/65/66/67/68 pinning ball A1 index area LPC2364FET100/LPC2368FET100 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aad225 Transparent top view Fig 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.2 Pin description Table 4.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 4. Pin description …continued Symbol Pin Ball Type Description P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 76[1] A10[1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 4. Pin description …continued Symbol Pin Ball Type Description P0[21]/RI1/ MCIPWR/RD1 57[1] G8[1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. O MCIPWR — Power Supply Enable for external SD/MMC power supply. (LPC2367/68 only) I RD1 — CAN1 receiver input. (LPC2364/66/68 only) I/O P0[22] — General purpose digital input/output pin.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 4. Pin description …continued Symbol Pin Ball Type Description P1[0]/ ENET_TXD0 95[1] D5[1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. P1[1]/ ENET_TXD1 94[1] B4[1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. P1[4]/ ENET_TX_EN 93[1] A4[1] I/O P1[4] — General purpose digital input/output pin.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 4. Pin description …continued Symbol Pin Ball Type Description P1[23]/PWM1[4]/ MISO0 37[1] K5[1] I/O P1[23] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/PWM1[5]/ MOSI0 38[1] I/O P1[24] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 4. Pin description …continued Symbol Pin Ball Type Description P2[3]/PWM1[4]/ DCD1/ PIPESTAT2 70[1] E7[1] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O PIPESTAT2 — Pipeline Status, bit 2. P2[4]/PWM1[5]/ DSR1/ TRACESYNC 69[1] I/O P2[4] — General purpose digital input/output pin.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 4. Pin description …continued Symbol Pin Ball Type Description P2[12]/EINT2/ MCIDAT2/ I2STX_WS 51[6] K10[6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. O MCIDAT2 — Data line for SD/MMC interface. (LPC2367/68 only) I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 4. Pin description …continued Symbol Pin Ball Type Description RSTOUT 14 - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2364/65/66/67/68 being in Reset state. Note: This pin is available in LPC2364FBD100, LPC2365FBD100, LPC2366FBD100, LPC2367FBD100, and LPC2368FBD100 devices only (LQFP100 package).
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers [12] If the RTC is not used, these pins can be left floating. [13] Pad provides special analog functionality. [14] Pad provides special analog functionality. [15] Pad provides special analog functionality. [16] Pad provides special analog functionality. [17] Pad provides special analog functionality. 7. Functional description 7.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • The standard 32-bit ARM set • A 16-bit Thumb set The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 0xFFFF FFFF 4.0 GB AHB PERIPHERALS 0xF000 0000 3.75 GB APB PERIPHERALS 3.5 GB 0xE000 0000 3.0 GB 0xC000 0000 RESERVED ADDRESS SPACE 2.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.8.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • Double buffer implementation for Bulk and Isochronous endpoints. 7.11 CAN controller and acceptance filters (LPC2364/66/68 only) The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7.13 10-bit DAC The DAC allows the LPC2364/65/66/67/68 to generate a variable analog output. The maximum output value of the DAC is Vi(VREF). 7.13.1 Features • • • • • 10-bit DAC Resistor string architecture Buffered output Power-down mode Selectable output drive 7.14 UARTs The LPC2364/65/66/67/68 each contain four UARTs.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7.16 SSP serial I/O controller The LPC2364/65/66/67/68 each contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7.18.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. • I2C1 and I2C2 use standard I/O pins and do not support powering off of individual devices connected to the same bus lines. • • • • • Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master).
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7.20 General purpose 32-bit timers/external event counters The LPC2364/65/66/67/68 include four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • • • • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  232  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the Internal RC oscillator (IRC), or the APB peripheral clock.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7.24.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy. Upon power-up or any chip reset, the LPC2364/65/66/67/68 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.24.1.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. The customers need to reconfigure the PLL and clock dividers accordingly. 7.24.4.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7.25.3 Code security (Code Read Protection - CRP) This feature of the LPC2364/65/66/67/68 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7.25.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM or the SRAM. This allows code running in different memory spaces to have control of the interrupts. 7.26 Emulation and debugging The LPC2364/65/66/67/68 support emulation and debugging via a JTAG serial port.
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NXP Semiconductors LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.26.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +5.1 V [2] 0.5 +6.0 V other I/O pins [2][3] 0.5 VDD(3V3) + 0.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 10. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 V) 3.0 3.3 3.6 V VDDA analog 3.3 V pad supply voltage 3.0 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); - - 100 mA 0 - 5.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 8. Static characteristics …continued Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit 0 V < VI < 3.3 V - - 10 A - - 5.25 V USB pins (LPC2364/66/68 only) IOZ OFF-state output current VBUS bus supply voltage VDI differential input sensitivity voltage (D+)  (D) 0.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 10.1 Power-down mode 002aae049 4 IDD(IO) (μA) 2 VDD(3V3) = 3.3 V VDD(3V3) = 3.0 V 0 −2 −4 −40 −15 10 35 60 85 temperature (°C) Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C. Fig 5. I/O maximum supply current IDD(IO) versus temperature in Power-down mode 002aae050 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 002aae051 800 IDD(DCDC)pd(3v3) (μA) 600 400 VDD(DCDC)(3V3) = 3.3 V 200 0 −40 VDD(DCDC)(3V3) = 3.0 V −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C. Fig 7. Total DC-to-DC converter supply current IDD(DCDC)pd(3V3) at different temperatures in Power-down mode 10.2 Deep power-down mode 002aae046 300 IDD(IO) (μA) 200 100 VDD(3V3) = 3.3 V VDD(3V3) = 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 002aae047 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C Fig 9. RTC battery maximum supply current IBAT versus temperature in Deep power-down mode 002aae048 100 IDD(DCDC)dpd(3v3) (μA) 80 60 VDD(DCDC)(3V3) = 3.3 V 40 VDD(DCDC)(3V3) = 3.0 V 20 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 10.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(3V3) = 3.3 V; standard port pins. Fig 11. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(3V3) = 3.3 V; standard port pins. Fig 12.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 11. Dynamic characteristics Table 9. Dynamic characteristics Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit 1 - 72 MHz 1 - 60 MHz 3.96 4 4.04 MHz 3.98 4.02 4.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 11.1 Internal oscillators Table 10. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 3.0 V  VDD(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz Max Unit [1] Parameters are valid over operating temperature range unless otherwise specified.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 11.4 Flash memory Table 13. Dynamic characteristics of flash Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified; VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 11.5 Timing TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 14. Differential data-to-EOP transition skew and EOP width shifting edges SCK sampling edges MOSI MISO tsu(SPI_MISO) 002aad326 Fig 15.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 12. ADC electrical characteristics Table 14. ADC characteristics VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C, unless otherwise specified; ADC frequency 4.5 MHz.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = Vi(VREF) − VSSA 1024 002aae604 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers LPC23XX 20 kΩ AD0[y] AD0[y]SAMPLE 3 pF Rvsi 5 pF VEXT VSS 002aac610 Fig 17. Suggested ADC interface - LPC2364/65/66/67/68 AD0[y] pin LPC2364_65_66_67_68 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 16 October 2013 © NXP B.V. 2013. All rights reserved.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 13. DAC electrical characteristics Table 15. DAC electrical characteristics VDDA = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter ED Conditions Min Typ Max Unit differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers VDD(3V3) R2 LPC23XX USB_UP_LED R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSS 002aac579 Fig 19. LPC2364/66/68 USB interface on a bus-powered device 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers LPC2xxx L XTAL1 XTAL2 = CL CP XTAL RS CX2 CX1 002aag469 Fig 21. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 16.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 14.3 RTC 32 kHz oscillator component selection LPC2xxx L RTCX1 RTCX2 = CL CP 32 kHz XTAL RS CX1 CX2 002aaf495 Fig 22. RTC oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation The RTC external oscillator circuit is shown in Figure 22.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 14.5 Standard I/O pin configuration Figure 23 shows the possible pin modes for standard I/O pins with analog input function: • • • • Digital output driver Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Analog input (for ADC input channels) The default configuration for standard I/O pins is input with pull-up enabled.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 14.6 Reset pin configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 24. Reset pin configuration LPC2364_65_66_67_68 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 16 October 2013 © NXP B.V. 2013. All rights reserved.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 15. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm B D SOT926-1 A ball A1 index area A2 E A A1 detail X e1 e ∅v ∅w b 1/2 e C M M C A B C y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 16. Abbreviations Table 19.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 17. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2364_65_66_67_68 v.7.1 20131016 Product data sheet - LPC2364_65_66_67_68 v.7 Modifications: LPC2364_65_66_67_68 v.7 Modifications: • • Product data sheet Table 9 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40. 20111020 Product data sheet - LPC2364_65_66_67_68 v.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 20. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC2364_65_66_67_68 v.6 20100201 Product data sheet - LPC2364_65_66_67_68 v.5 Modifications: LPC2364_65_66_67_68 v.5 Modifications: • • • Table 5 “Limiting values”: Changed VESD min/max to 2500/+2500. Table 6: Updated min, typical and max values for oscillator pins.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 20. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.10.2 7.11 7.11.1 7.12 7.12.1 7.13 7.13.1 7.14 7.14.1 7.15 7.15.1 7.16 7.16.1 7.17 7.17.1 7.18 7.18.1 7.19 7.19.1 7.20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC2364/65/66/67/68 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 14.1 14.2 14.3 14.4 14.5 14.6 15 16 17 18 18.1 18.2 18.3 18.4 19 20 Suggested USB interface solutions (LPC2364/66/68 only). . . . . . . . . . . . . . . . . . . Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTC 32 kHz oscillator component selection . . XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . .