Datasheet

LPC2361_62 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5.1 — 15 October 2013 14 of 65
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers
high performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed complex
instruction set computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set
• A 16-bit Thumb set
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
7.2 On-chip flash programming memory
The LPC2361/2362 incorporate a 64 kB and 128 kB flash memory system respectively.
This memory may be used for both code and data storage. Programming of the flash
memory may be accomplished in several ways. It may be programmed In System via the
serial port (UART0). The application program may also erase and/or program the flash
while the application is running, allowing a great degree of flexibility for data storage field
and firmware upgrades.
The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to
allow it to operate at SRAM speeds of 72 MHz.
7.3 On-chip SRAM
The LPC2361/2362 include SRAM memory of 8 kB (LPC2361) or 32 kB (LPC2362),
reserved for the ARM processor exclusive use. This RAM may be used for code and/or
data storage and may be accessed as 8 bits, 16 bits, and 32 bits.
A 16 kB SRAM block serving as a buffer for the Ethernet controller (available as general
purpose SRAM for the LPC2361) and an 8 kB SRAM used by the GPDMA controller or
the USB device can be used both for data and code storage. The 2 kB RTC SRAM can be
used for data storage only. The RTC SRAM is battery powered and retains the content in
the absence of the main power supply.