Datasheet

LPC2212_2214 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 14 June 2011 38 of 47
NXP Semiconductors
LPC2212/2214
Single-chip 16/32-bit ARM microcontrollers
Table 10. External memory interface dynamic characteristics
C
L
=25pF; T
amb
=40  C.
Symbol Parameter Conditions Min Typ Max Unit
Common to read and write cycles
t
CHAV
XCLK HIGH to address valid
time
--10ns
t
CHCSL
XCLK HIGH to CS LOW time - - 10 ns
t
CHCSH
XCLK HIGH to CS HIGH
time
--10ns
t
CHANV
XCLK HIGH to address
invalid time
--10ns
Read cycle parameters
t
CSLAV
CS LOW to address valid
time
[1]
5-+10ns
t
OELAV
OE LOW to address valid
time
[1]
5-+10ns
t
CSLOEL
CS LOW to OE LOW time 5-+5ns
t
am
memory access time
[2][3]
(T
cy(CCLK)
 (2 + WST1)) +
(20)
-- ns
t
am(ibr)
memory access time (initial
burst-ROM)
[2][3]
(T
cy(CCLK)
 (2 + WST1)) +
(20)
-- ns
t
am(sbr)
memory access time
(subsequent burst-ROM)
[2][4]
T
cy(CCLK)
+(20) - - ns
t
h(D)
data input hold time
[5]
0--ns
t
CSHOEH
CS HIGH to OE HIGH time 5-+5ns
t
OEHANV
OE HIGH to address invalid
time
5-+5ns
t
CHOEL
XCLK HIGH to OE LOW time 5-+5ns
t
CHOEH
XCLK HIGH to OE HIGH
time
5-+5ns
Write cycle parameters
t
AVCSL
address valid to CS LOW
time
[1]
T
cy(CCLK)
 10 - - ns
t
CSLDV
CS LOW to data valid time 5-+5ns
t
CSLWEL
CS LOW to WE LOW time 5-+5ns
t
CSLBLSL
CS LOW to BLS LOW time 5-+5ns
t
WELDV
WE LOW to data valid time 5-+5ns
t
CSLDV
CS LOW to data valid time 5-+5ns
t
WELWEH
WE LOW to WE HIGH time
[2]
T
cy(CCLK)
 (1 + WST2)  5- T
cy(CCLK)
 (1 +
WST2) + 5
ns
t
BLSLBLSH
BLS LOW to BLS HIGH time
[2]
T
cy(CCLK)
 (1 + WST2)  5- T
cy(CCLK)

(1 + WST2) + 5
ns
t
WEHANV
WE HIGH to address invalid
time
[2]
T
cy(CCLK)
 5-T
cy(CCLK)
+5 ns
t
WEHDNV
WE HIGH to data invalid time
[2]
(2  T
cy(CCLK)
)  5-(2 T
cy(CCLK)
)+5 ns
t
BLSHANV
BLS HIGH to address invalid
time
[2]
T
cy(CCLK)
 5-T
cy(CCLK)
+5 ns