Datasheet

LPC2109_2119_2129 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 14 June 2011 11 of 46
NXP Semiconductors
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
However, the ISP flash erase command can be executed at any time (no matter whether
the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user flash.
With the CRP off, full access to the chip via the JTAG and/or ISP is restored.
6.3 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8 bit, 16 bit, and 32 bit. The LPC2109/2119/2129 provide 8 kB of SRAM for the
LPC2109 and 16 kB for the LPC2119 and LPC2129.
6.4 Memory map
The LPC2109/2119/2129 memory maps incorporate several distinct regions, as shown in
Figure 3
.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip SRAM. This is described in Section 6.18 “
System
control”.