Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 16/32-Bit 70 MHz I/O number 32

1. General description

The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with

real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of

embedded high-speed ﬂash memory. A 128-bit wide memory interface and a unique

accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical performance in interrupt service routines and DSP algorithms, this increases

performance up to 30 % over Thumb mode. For critical code size applications, the

alternative 16-bit Thumb mode reduces code by more than 30 % with minimal

performance penalty.

Due to their tiny size and low power consumption, the LPC2101/02/03 are ideal for

applications where miniaturization is a key requirement. A blend of serial communications

interfaces ranging from multiple UARTs, SPI to SSP and two I

C-buses, combined with

on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication

gateways and protocol converters. The superior performance also makes these devices

suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved

10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with

up to nine edge or level sensitive external interrupt pins make these microcontrollers

particularly suitable for industrial control and medical systems.

2. Features

2.1 Enhanced features

Enhanced features are available in parts LPC2101/02/03 labelled Revision A and higher:

n Deep power-down mode with option to retain SRAM memory and/or RTC.

n Three levels of ﬂash Code Read Protection (CRP) implemented.

2.2 Key features

n 16-bit/32-bit ARM7TDMI-S microcontroller in tiny LQFP48 and HVQFN48 packages.

n 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip ﬂash program

memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.

n ISP/IAP via on-chip bootloader software. Single ﬂash sector or full chip erase in

100 ms and programming of 256 bytes in 1 ms.

n EmbeddedICE-RT offers real-time debugging with the on-chip RealMonitor software.

n The 10-bit ADC provides eight analog inputs, with conversion times as low as 2.44 µs

per channel and dedicated result registers to minimize interrupt overhead.

n Two 32-bit timers/external event counters with combined seven capture and seven

compare channels.

LPC2101/02/03

Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB

ﬂash with ISP/IAP, fast ports and 10-bit ADC

Rev. 04 — 2 June 2009 Product data sheet

Summary of content (37 pages)

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LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC Rev. 04 — 2 June 2009 Product data sheet 1. General description The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded high-speed flash memory.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers n Two 16-bit timers/external event counters with combined three capture and seven compare channels. n Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input. n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. n Vectored interrupt controller with configurable priorities and vector addresses.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 4.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 5. Pinning information 37 P0.12/DSR1/MAT1.0/AD0.5 38 P0.25/AD0.6 39 P0.26/AD0.7 40 VDD(3V3) 41 P0.13/DTR1/MAT1.1 42 VDDA 43 VSS 44 P0.14/DCD1/SCK1/EINT1 45 P0.15/RI1/EINT2 46 P0.16/EINT0/MAT0.2 47 P0.17/CAP1.2/SCL1 48 P0.18/CAP1.3/SDA1 5.1 Pinning P0.19/MAT1.2/MISO1 1 36 P0.11/CTS1/CAP1.1/AD0.4 P0.20/MAT1.3/MOSI1 2 35 P0.10/RTS1/CAP1.0/AD0.3 P0.21/SSEL1/MAT3.0 3 34 P0.24/AD0.2 VBAT 4 33 P0.23/AD0.
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LPC2101/02/03 NXP Semiconductors 37 P0.12/DSR1/MAT1.0/AD0.5 38 P0.25/AD0.6 40 VDD(3V3) 39 P0.26/AD0.7 41 P0.13/DTR1/MAT1.1 43 VSS 42 VDDA 44 P0.14/DCD1/SCK1/EINT1 45 P0.15/RI1/EINT2 46 P0.16/EINT0/MAT0.2 terminal 1 index area 47 P0.17/CAP1.2/SCL1 48 P0.18/CAP1.3/SDA1 Single-chip 16-bit/32-bit microcontrollers P0.19/MAT1.2/MISO1 1 36 P0.11/CTS1/CAP1.1/AD0.4 P0.20/MAT1.3/MOSI1 2 35 P0.10/RTS1/CAP1.0/AD0.3 P0.21/SSEL1/MAT3.0 3 34 P0.24/AD0.2 VBAT 4 33 P0.23/AD0.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 5.2 Pin description Table 3. Pin description Symbol Pin P0.0 to P0.31 P0.0/TXD0/ MAT3.1 13[1] P0.1/RXD0/ MAT3.2 14[1] P0.2/SCL0/ CAP0.0 18[2] P0.3/SDA0/ MAT0.0 21[2] P0.4/SCK0/ CAP0.1 22[1] P0.5/MISO0/ MAT0.1 23[1] P0.6/MOSI0/ CAP0.2 24[1] P0.7/SSEL0/ MAT2.0 28[1] P0.8/TXD1/ MAT2.1 29[1] P0.9/RXD1/ MAT2.2 30[1] P0.10/RTS1/ CAP1.0/AD0.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P0.11/CTS1/ CAP1.1/AD0.4 36[3] I/O P0.11 — General purpose input/output digital pin. I CTS1 — Clear to Send input for UART1. I CAP1.1 — Capture input for Timer 1, channel 1. I AD0.4 — ADC 0, input 4. I/O P0.12 — General purpose input/output digital pin. I DSR1 — Data Set Ready input for UART1. O MAT1.0 — PWM output for Timer 1, channel 0.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P0.22/AD0.0 32[3] I/O P0.22 — General purpose input/output digital pin. I AD0.0 — ADC 0, input 0. P0.23/AD0.1 33[3] I/O P0.23 — General purpose input/output digital pin. I AD0.1 — ADC 0, input 1. P0.24/AD0.2 34[3] I/O P0.24 — General purpose input/output digital pin. I AD0.2 — ADC 0, input 2. P0.25/AD0.6 38[3] I/O P0.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description VSS 7, 19, 43 I Ground: 0 V reference. VSSA 31 I Analog ground: 0 V reference. This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. VDDA 42 I Analog 3.3 V power supply: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6. Functional description 6.1 Architectural overview The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC).
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2 kB, 4 kB or 8 kB of static RAM. 6.4 Memory map The LPC2101/02/03 memory map incorporates several distinct regions, as shown in Figure 4.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.5 Interrupt controller The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 6.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. 6.12 SSP serial I/O controller The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.14 General purpose 16-bit timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • • • • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (TPCLK × 256 × 4) to (TPCLK × 232 × 4) in multiples of TPCLK × 4. 6.16 Real-time clock The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.17.3 Reset and wake-up timer Reset has two sources on the LPC2101/02/03: the RST pin and watchdog reset. The RST pin is a Schmitt trigger input pin with an additional glitch filter.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.17.4 Code security (Code Read Protection - CRP) This feature of the LPC2101/02/03 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. Implemented in bootloader code version 2.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.18.1 EmbeddedICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the remote debug protocol commands to the JTAG data needed to access the ARM core. The ARM core has a debug communication channel function built-in.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Min Max Unit supply voltage (1.8 V) [2] −0.5 +2.5 V VDD(3V3) supply voltage (3.3 V) [3] −0.5 +4.6 V VDDA analog 3.3 V pad supply voltage −0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT VDD(1V8) Parameter Conditions −0.5 +4.6 V [4] −0.5 +5.1 V [5][6] −0.5 +6.0 V [5] −0.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 8. Static characteristics Table 5. Static characteristics Tamb= −40 °C to +85 °C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit 1.65 1.8 1.95 V 2.6[4] 3.3 3.6 V VDD(1V8) supply voltage (1.8 V) [2] VDD(3V3) supply voltage (3.3 V) [3] VDDA analog 3.3 V pad supply voltage 2.6[5] 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT 2.0[6] 3.3 3.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 5. Static characteristics …continued Tamb= −40 °C to +85 °C for commercial applications, unless otherwise specified. Symbol Ipu Parameter pull-up current Min Typ[1] Max Unit −15 −50 −85 µA 0 0 0 µA - 41 70 mA VDD(1V8) = 1.8 V; Tamb = 25 °C - 2.5 25 µA VDD(1V8) = 1.8 V; Tamb = 85 °C - 35 105 µA - 0.7 - µA - 10 15 µA VDD(1V8) = 1.8 V; Vi(VBAT) = 2.5 V - 7 12 µA VDD(1V8) = 1.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 5. Static characteristics …continued Tamb= −40 °C to +85 °C for commercial applications, unless otherwise specified. Min Typ[1] Max Unit output voltage on pin XTAL2 0 - 1.8 V input voltage on pin RTCX1 0 - 1.8 V 0 - 1.8 V Symbol Parameter Vo(XTAL2) Vi(RTCX1) Conditions Vo(RTCX2) output voltage on pin RTCX2 [1] Typical ratings are not guaranteed.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 offset error EO 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) 1 LSB = VDDA − VSSA 1024 002aac046 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 8.1 Power consumption in Deep power-down mode 002aae680 1.5 IDD(CORE) (µA) 1.25 1 VDD(1V8) =1.8 V 1.7 V 0.75 1.65 V 0.5 −40 −15 10 35 60 85 Temperature (°C) Test conditions: Deep power-down mode entered; RTC off; SRAM off; Vi(VBAT) = VDD(3V3) = VDDA = 3.3 V. Fig 6. Core supply current IDD(CORE) measured at different temperatures and supply voltages 002aae681 15 IBAT (µA) RTC on; SRAM on RTC on; SRAM off 12.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 002aae682 0.20 IDD(IO) (µA) 0.15 0.10 0.05 0 −40 −15 10 35 60 85 Temperature (°C) Test conditions: Deep power-down mode entered; RTC off; SRAM off; VDD(3V3) = 3.3 V; VDD(1V8) = 1.8 V; Vi(BAT) = VDDA = 3.3 V. Fig 8. I/O supply current IDD(IO) measured at different temperatures LPC2101_02_03_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 9. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 0 °C to 70 °C for commercial applications, −40 °C to +85 °C for industrial applications, VDD(1V8), VDD(3V3) over specified ranges[1]. Symbol Parameter Conditions Min Typ[2] Max Unit External clock fosc oscillator frequency 10 - 25 MHz Tcy(clk) clock cycle time 40 - 100 ns tCHCX clock HIGH time Tcy(clk) × 0.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 10.2 XTAL and RTC Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1 and Cx2, and Cx3 in case of third overtone crystal usage, have a common ground plane. The external components must also be connected to the ground plain.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm D SOT619-7 A B terminal 1 index area E A A1 c detail X e1 C e 1/2 e v w b 13 M M y1 C C A B C y 24 L 25 12 e e2 Eh 1/2 e 1 36 terminal 1 index area 48 37 X Dh 0 2.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm A B D SOT778-3 terminal 1 index area E A A1 c detail X C e1 e v w b 1/2 e 13 M M y1 C C A B C y 24 L 25 12 e e2 Eh 1/2 e 1 terminal 1 index area 36 48 37 X Dh 0 2.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 12. Abbreviations Table 8.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 13. Revision history Table 9. Revision history Document ID Release date Data sheet status LPC2101_02_03_4 20090602 Product data sheet Modifications: LPC2101_02_03_3 Section 6.17.4 “Code security (Code Read Protection - CRP)”: added description of three CRP levels (applicable to Revision A and higher). • Section 6.17.7 “Power control”: added description of Deep power-down mode (applicable to Revision A and higher).
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC2101/02/03 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 16. Contents 1 2 2.1 2.2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 6.7 6.7.1 6.8 6.8.1 6.9 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.17.2 6.17.3 6.17.4 6.17.5 6.17.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Enhanced features . . . . . . . . . . . . . . . . . . . .