Datasheet

LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 88 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
11.6 SSP interface
[1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited
by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster
than that. At and below the maximum frequency, T
cy(clk)
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
main
.
5The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the main clock frequency f
main
, the
SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register),
and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] T
amb
= 40 C to 85 C; V
DD(3V3)
= 3.0 V to 3.6 V.
[3] T
cy(clk)
= 12  T
cy(PCLK)
. The maximum clock rate in slave mode is 1/12th of the PCLK rate.
[4] T
amb
= 25 C; V
DD(3V3)
= 3.3 V.
Table 24. Dynamic characteristics: SSP pins in SPI mode
C
L
=10pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
SSP master
T
cy(clk)
clock cycle time full-duplex
mode
[1]
30 - ns
when only
transmitting
30 - ns
t
DS
data set-up time in SPI mode
[2]
14.8 - ns
t
DH
data hold time in SPI mode
[2]
2- ns
t
v(Q)
data output valid time in SPI mode
[2]
-6.3ns
t
h(Q)
data output hold time in SPI mode
[2]
2.4 - ns
SSP slave
T
cy(clk)
clock cycle time
[3]
100 - ns
t
DS
data set-up time in SPI mode
[3][4]
14.8 - ns
t
DH
data hold time in SPI mode
[3][4]
2- ns
t
v(Q)
data output valid time in SPI mode
[3][4]
-6.3ns
t
h(Q)
data output hold time in SPI mode
[3][4]
2.4 - ns