Datasheet

LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 86 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user
manual for details.
Fig 19. Dynamic external memory interface signal timing
002aah129
T
cy(clk)
EMC_CLKn
delay = 0
EMC_DYCSn,
EMC_RAS,
EMC_CAS,
EMC_WE,
EMC_CKEOUTn,
EMC_A[22:0],
EMC_DQMOUTn
t
h(Q)
t
h(D)
t
su(D)
EMC_D[31:0]
write
EMC_D[31:0]
read
t
d(QV)
t
h(x)
t
d(xV)
Table 20. Dynamic characteristics: Dynamic external memory interface programmable
clock delays
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V.Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
t
d
delay time Programmable delay block 0 (CMDDLY
or CLKOUTnDLY bit 0 = 1)
[1]
0.1 0.2 ns
Programmable delay block 1 (CMDDLY
or CLKOUTnDLY bit 1 = 1)
[1]
0.2 0.5 ns
Programmable delay block 2 (CMDDLY
or CLKOUTnDLY bit 2 = 1)
[1]
0.5 1.3 ns
Programmable delay block 3 (CMDDLY
or CLKOUTnDLY bit 3 = 1)
[1]
1.2 2.9 ns
Programmable delay block 4 (CMDDLY
or CLKOUTnDLY bit 4 = 1)
[1]
2.4 6.0 ns