Datasheet
LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 84 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
[1] Refers to SDRAM clock signal EMC_CLKx.
[2] CLKDLY = CLKOUTnDLY, where n = 0, 1.
[3] The data input set-up time has to be selected with the following margin:
t
su(D)
+ delay time of feedback clock SDRAM access time board delay time 0.
[4] The data input hold time has to be selected with the following margin:
t
h(D)
+ SDRAM access time board delay time delay time of feedback clock 0.
Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00
C
L
=30pF, T
amb
=
40
C to 85
C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Min Typ Max Unit
Common to read and write cycles
T
cy(clk)
clock cycle time
[1]
12.5 - - ns
t
d(SV)
chip select valid delay time
[2]
(CLKDLY + 1)
0.25 + 4.1
(CLKDLY + 1)
0.25 + 5.7
(CLKDLY + 1)
0.25 + 8.4
ns
t
h(S)
chip select hold time
[2]
(CLKDLY + 1)
0.25 + 0.5
(CLKDLY + 1)
0.25 + 1.1
(CLKDLY + 1)
0.25 + 2.7
ns
t
d(RASV)
row address strobe valid delay
time
[2]
(CLKDLY + 1)
0.25 + 4.2
(CLKDLY + 1)
0.25 + 5.8
(CLKDLY + 1)
0.25 + 8.4
ns
t
h(RAS)
row address strobe hold time
[2]
(CLKDLY + 1)
0.25 + 0.6
(CLKDLY + 1)
0.25 + 1.2
(CLKDLY + 1)
0.25 + 2.9
ns
t
d(CASV)
column address strobe valid
delay time
[2]
(CLKDLY + 1)
0.25 + 4.2
(CLKDLY + 1)
0.25 + 5.8
(CLKDLY + 1)
0.25 + 8.4
ns
t
h(CAS)
column address strobe hold
time
[2]
(CLKDLY + 1)
0.25 + 0.6
(CLKDLY + 1)
0.25 + 1.2
(CLKDLY + 1)
0.25 + 2.9
ns
t
d(WV)
write valid delay time
[2]
(CLKDLY + 1)
0.25 + 4.9
(CLKDLY + 1)
0.25 + 6.6
(CLKDLY + 1)
0.25 + 9.9
ns
t
h(W)
write hold time
[2]
(CLKDLY + 1)
0.25 + 0.9
(CLKDLY + 1)
0.25 + 1.7
(CLKDLY + 1)
0.25 + 3.6
ns
t
d(AV)
address valid delay time
[2]
(CLKDLY + 1)
0.25 + 4.7
(CLKDLY + 1)
0.25 + 6.6
(CLKDLY + 1)
0.25 + 9.6
ns
t
h(A)
address hold time
[2]
(CLKDLY + 1)
0.25 + 0.4
(CLKDLY + 1)
0.25 + 0.8
(CLKDLY + 1)
0.25 + 2.4
ns
Read cycle parameters
t
su(D)
data input set-up time
[3]
(FBCLKDLY + 1)
0.25 + 0.3
(FBCLKDLY + 1)
0.25 + 3.1
-ns
t
h(D)
data input hold time
[4]
(FBCLKDLY + 1)
0.25 + 3.7
(FBCLKDLY + 1)
0.25 + 4.3
(FBCLKDLY + 1)
0.25 + 5.2
ns
Write cycle parameters
t
d(QV)
data output valid delay time
[2]
(CLKDLY + 1)
0.25 + 4.8
(CLKDLY + 1)
0.25 + 6.8
(CLKDLY + 1)
0.25 + 9.8
ns
t
h(Q)
data output hold time
[2]
(CLKDLY + 1)
0.25 0.4
(CLKDLY + 1)
0.25 + 0
(CLKDLY + 1)
0.25 + 1.1
ns