Datasheet

LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 81 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
11.2 External memory interface
Table 17. Dynamic characteristics: Static external memory interface
C
L
=30pF, T
amb
=  40  C to 85  C, V
DD(3V3)
= 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter
[1]
Conditions
[1]
Min Typ Max Unit
Read cycle parameters
[2]
t
CSLAV
CS LOW to address
valid time
RD
1
2.7 3.5 4.7 ns
t
CSLOEL
CS LOW to OE LOW
time
RD
2
[3]
2.7 + T
cy(clk)

WAITOEN
3.4 + T
cy(clk)

WAITOEN
4.6 + T
cy(clk)

WAITOEN
ns
t
CSLBLSL
CS LOW to BLS LOW
time
RD
3
; PB = 1
[3]
2.8 3.8 5.1 ns
t
OELOEH
OE LOW to OE HIGH
time
RD
4
[3]
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 2.26
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 2.83
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 3.7
ns
t
am
memory access time RD
5
[3]
[4]
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 8.6
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 11.9
(WAITRD 
WAITOEN + 1) 
T
cy(clk)
 18.0
ns
t
h(D)
data input hold time RD
6
[3]
[5]
4.1 5.8 - ns
t
CSHBLSH
CS HIGH to BLS HIGH
time
PB = 1 2.8 3.7 5.1 ns
t
CSHOEH
CS HIGH to OE HIGH
time
[3]
2.7 3.5 4.6 ns
t
OEHANV
OE HIGH to address
invalid time
[3]
0.1 0.1 0.16 ns
t
deact
deactivation time RD
7
[3]
- 3.4 4.7 ns
Write cycle parameters
[2]
t
CSLAV
CS LOW to address
valid time
WR
1
2.7 3.5 4.7 ns
t
CSLDV
CS LOW to data valid
time
WR
2
2.8 3.9 5.1 ns
t
CSLWEL
CS LOW to WE LOW
time
WR
3
; PB =1
[3]
2.7 + T
cy(clk)

(1 + WAITWEN)
3.5 + T
cy(clk)

(1 + WAITWEN)
4.6 + T
cy(clk)

(1 + WAITWEN)
ns
t
CSLBLSL
CS LOW to BLS LOW
time
WR
4
; PB = 1
[3]
2.8 3.9 5.1 ns
t
WELWEH
WE LOW to WE HIGH
time
WR
5
; PB =1
[3]
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
 2.3
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
 2.8
(WAITWR 
WAITWEN + 1) 
T
cy(clk)
 3.8
ns
t
BLSLBLSH
BLS LOW to BLS HIGH
time
PB = 1
[3]
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 2.6
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 3.4
(WAITWR 
WAITWEN + 3) 
T
cy(clk)
 4.9
ns
t
WEHDNV
WE HIGH to data
invalid time
WR
6
; PB =1
[3]
2.5 + T
cy(clk)
3.3 + T
cy(clk)
4.3 + T
cy(clk)
ns
t
WEHEOW
WE HIGH to end of
write time
WR
7
; PB = 1
[3][6]
T
cy(clk)
 2.7 T
cy(clk)
 3.4 T
cy(clk)
 4.6 ns
t
BLSHDNV
BLS HIGH to data
invalid time
PB = 1 2.7 3.6 4.8 ns
t
WEHANV
WE HIGH to address
invalid time
PB = 1
[3]
2.4 + T
cy(clk)
3.0 + T
cy(clk)
3.9 + T
cy(clk)
ns