Datasheet

LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 40 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7. Functional description
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus. The I-code and D-code core buses are faster than the system bus and
are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for
instruction fetch (I-code) and one bus for data access (D-code). The use of two core
buses allows for simultaneous operations if concurrent operations target different devices.
Row J
1 RESET
2 RTCX1 3 RTCX2 4 P0[12]
5 P0[13] 6 - 7 - 8 -
9 - 10 P0[19] 11 P4[8] 12 P0[17]
13 P0[18] 14 V
DD(3V3)
--
Row K
1 VBAT 2 P1[31] 3 P1[30] 4 XTAL2
5 P0[29] 6 P1[20] 7 P3[26] 8 V
DD(3V3)
9 P4[3] 10 P4[6] 11 P0[21] 12 P4[7]
13 P4[26] 14 P0[20] - -
Row L
1 P2[29] 2 XTAL1 3 P0[27] 4 V
DD(3V3)
5 P1[18] 6 P4[0] 7 P1[25] 8 V
SSREG
9V
SS
10 P0[10] 11 V
DD(3V3)
12 P5[2]
13 V
SS
14 P0[22] - -
Row M
1 P0[28] 2 P2[28] 3 P3[25] 4 P3[23]
5 P0[14] 6 P1[22] 7 P4[1] 8 P4[2]
9 P1[27] 10 P0[0] 11 P2[13] 12 P2[11]
13 P2[10] 14 P4[19] - -
Row N
1 P0[31] 2 USB_D-2 3 P3[24] 4 P0[30]
5 P2[19] 6 P1[21] 7 P1[23] 8 P2[21]
9V
DD(REG)(3V3)
10 P1[29] 11 P0[1] 12 P4[16]
13 P4[17] 14 P2[12] - -
Row P
1 P2[24] 2 P2[25] 3 P2[18] 4 V
SS
5 P1[19] 6 P2[20] 7 P1[24] 8 P1[26]
9 P2[16] 10 P1[28] 11 P2[17] 12 P0[11]
13 P4[4] 14 P4[18] - -
Table 5. Pin allocation table TFBGA180
Not all functions are available on all parts. See Table 2
and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball Symbol