Datasheet
LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 33 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P5[3] 141 G14 G10 98
[11]
I I/O P5[3] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I U4_RXD — Receiver input for USART4.
I/O I2C0_SCL — I
2
C0 clock input/output (this pin uses a
specialized I
2
C pad that supports I
2
C Fast Mode Plus).
P5[4] 206 C3 C4 143
[3]
I;
PU
I/O P5[4] — General purpose digital input/output pin.
O U0_OE — RS-485/EIA-485 output enable signal for UART0.
- R — Function reserved.
O T3_MAT3 — Match output for Timer 3, channel 3.
O U4_TXD — Transmitter output for USART4 (input/output in
smart card mode).
JTAG_TDO
(SWO)
2D3B11
[3]
O O Test Data Out for JTAG interface. Also used as Serial wire trace
output.
JTAG_TDI 4 C2 C3 3
[3]
I;
PU
I Test Data In for JTAG interface.
JTAG_TMS
(SWDIO)
6E3C24
[3]
I;
PU
I Test Mode Select for JTAG interface. Also used as Serial wire
debug data input/output.
JTAG_TRST
8D1D45
[3]
I;
PU
I Test Reset for JTAG interface.
JTAG_TCK
(SWDCLK)
10 E2 D2 7
[3]
i I Test Clock for JTAG interface. This clock must be slower than
1/6 of the CPU clock (CCLK) for the JTAG interface to operate.
Also used as serial wire clock.
RESET
35 M2 J1 24
[12]
I;
PU
I External reset input with 20 ns glitch filter. A LOW-going pulse
as short as 50 ns on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor
execution to begin at address 0. This pin also serves as the
debug select input. LOW level selects the JTAG boundary scan.
HIGH level selects the ARM SWD debug mode.
RSTOUT
29 K3 H2 20
[3]
OH O Reset status output. A LOW output on this pin indicates that the
device is in the reset state for any reason. This reflects the
RESET
input pin and all internal reset sources.
RTC_ALARM 37 N1 H5 26
[13]
OL O RTC controlled output. This pin has a low drive strength and is
powered by VBAT. It is driven HIGH when an RTC alarm is
generated.
RTCX1 34 K2 J2 23
[14]
[15]
- I Input to the RTC 32 kHz ultra-low power oscillator circuit.
RTCX2 36 L2 J3 25
[14]
[15]
- O Output from the RTC 32 kHz ultra-low power oscillator circuit.
USB_D252U1N237
[9]
- I/O USB port 2 bidirectional D line.
Table 3. Pin description
…continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state
[1]
Type
[2]
Description