Datasheet
LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 116 of 122
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
19. Revision history
Table 35. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC178X_7X v.5.1 20140909 Product data sheet - LPC178X_7X v.5
Modifications:
• Updated parameter t
su(D)
in Table 18 “Dynamic characteristics: Dynamic external memory
interface, read strategy bits (RD bits) = 00”: Minimum value changed to (FBCLKDLY + 1)
0.25 + 0.3. Maximum value removed.
• Removed max value from parameter t
h(D)
in Table 17.
• Removed min value from parameter t
deact
in Table 17.
• Specified ADC conversion rate in burst mode in Table 29 “12-bit ADC characteristics”.
LPC178X_7X v.5 20140501 Product data sheet - LPC178X_7X v.4.1
Modifications:
• Removed overbar from NMI.
• Table 3:
– Added minimum reset pulse width of 50 ns to RESET
pin.
– Updated Table note 14 for RTCX pins (32 kHz crystal must be used to operate RTC).
– Added boundary scan information to description for RESET
pin.
– Updated pin description of STCLK.
• Table 13: Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC
and DAC are not used.”.
• Table 23: Removed reference to RESET pin from Table note 1.
• Table 24:
– Removed T
cy(PCLK)
spec; already given by the maximum chip frequency.
– Changed min clock cycle time for SSP slave from 120 to 100.
– Updated Table note 1 and Table note 3.
• Table 29: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC
and DAC are not used.”.
• Section 7.21.1 “Features”: Changed max speed for SSP master from 60 to 33.
• and added typical specs Table 17, Table 18, Table 19.
• SOT570-2 obsolete; replaced with SOT570-3.
• Table 17:
– Updated EMC timing specs to CL = 30 pF.
– Added typical specs.
– Table note 3: Changed T
cy(clk)
= 1/CCLK to T
cy(clk)
= 1/EMC_CLK.
• Table 18:
– Updated EMC timing specs to CL = 30 pF
– Added typical specs.
– Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
• Table 19:
– Updated EMC timing specs to CL = 30 pF
– Added typical specs.
– Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
LPC178X_7X v.4.1 20121115 Product data sheet - LPC178X_7X v.4