Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 100 MHz I/O number 70

1. General description

The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for

embedded applications featuring a high level of integration and low power consumption.

The ARM Cortex-M3 is a next generation core that offers system enhancements such as

enhanced debug features and a higher level of support block integration.

The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The

LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU

incorporates a 3-stage pipeline and uses a Harvard architecture with separate local

instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3

CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of

flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG

interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP

controllers, SPI interface, 3 I

C-bus interfaces, 2-input plus 2-output I

S-bus interface,

8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface,

four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time

Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.

The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x

ARM7-based microcontroller series.

For additional documentation, see Section 19 “

References”.

2. Features and benefits

 ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

(LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit

(MPU) supporting eight regions is included.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator

enables high-speed 120 MHz operation with zero wait states.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 On-chip SRAM includes:

 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU

access.

LPC1769/68/67/66/65/64/63

32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and

64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

Rev. 9.5 — 24 June 2014 Product data sheet

Summary of content (89 pages)

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LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 9.5 — 24 June 2014 Product data sheet 1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption.
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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller       Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
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NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller                    1.  Quadrature encoder interface that can monitor one external quadrature encoder.  One standard PWM/timer block with external count input.  RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.  WatchDog Timer (WDT).
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 3. Applications  eMetering  Lighting  Industrial networking  Alarm systems  White goods  Motor control 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5. Marking The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC176x: Table 3.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 51 75 7.1 Pinning 76 50 LPC176xFBD100 26 1 25 100 Fig 2. 002aad945 Pin configuration LQFP100 package ball A1 index area LPC1768/65FET100 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aaf723 Transparent top view Fig 3. Pin configuration TFBGA100 package LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1768UK bump A1 index area 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K aaa-009522 Transparent top view Fig 4. Table 4.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin/ball P1[0] to P1[31] P1[0]/ ENET_TXD0 95 P1[1]/ ENET_TXD1 94 P1[4]/ ENET_TX_EN 93 P1[8]/ ENET_CRS 92 P1[9]/ ENET_RXD0 91 P1[10]/ ENET_RXD1 90 P1[14]/ ENET_RX_ER 89 P1[15]/ ENET_REF_CLK 88 P1[16]/ ENET_MDC 87 P1[17]/ ENET_MDIO 86 D5 B4 A4 C5 B5 A5 D6 C6 A6 B6 Type Description I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5. Pin description …continued Symbol Pin/ball LQFP100 TFBGA100 WLCSP100 32-bit ARM Cortex-M3 microcontroller TDO/SWO 1 A1 A1 [1][7] TDI 2 C3 C4 [1][8] B3 [1][8] TMS/SWDIO 3 B1 Type Description O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. I TDI — Test Data in for JTAG interface. I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors Table 5. Pin description …continued Symbol Pin/ball LQFP100 TFBGA100 WLCSP100 32-bit ARM Cortex-M3 microcontroller VREFN 15 F1 A6 VBAT 19 G2 A8 n.c. 13 D4, E4 B6, D6 [10][12] Type Description I ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. I RTC pin power supply: 3.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1).
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 0x400F C000 31 4 GB QEI 0x400B 8000 14 motor control PWM 0x400B 4000 13 reserved 0x400B 0000 12
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 8.10.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the part can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.13.1 Features • • • • • Two CAN controllers and buses. Data rates to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1. Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 8.18.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.20 I2S-bus serial I/O controllers Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 8.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 8.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • Includes lock/safe feature. 8.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller See Figure 6 for an overview of the LPC17xx clock generation.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC17xx to I/O pads VDD(3V3) to core VSS REGULATOR to memories, peripherals, oscillators, PLLs VDD(REG)(3V3) MAIN POWER DOMAIN POWER SELECTOR VBAT ULTRA LOW-POWER REGULATOR BACKUP REGISTERS RTCX1 32 kHz OSCILLATOR RTCX2 REAL-TIME CLOCK RTC POWER DOMAIN DAC VDDA VREFP ADC VREFN VSSA ADC POWER DOMAIN 002aad978 Fig 7. Power distribution 8.30 System control 8.30.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM blocks.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) Parameter Conditions supply voltage (3.3 V) external rail Min Max Unit [2] 0.5 +4.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V VDDA analog 3.3 V pad supply voltage [2] 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT [2] 0.5 +4.6 V [2] 0.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C) • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit 2.4 3.3 3.6 V 2.4 3.3 3.6 V [3][4] 2.5 3.3 3.6 V input voltage on pin VBAT [5] 2.1 3.3 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.5 3.3 VDDA V IDD(REG)(3V3) regulator supply current active mode; code (3.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IDD(ADC) Parameter ADC supply current Min Typ[1] Max Unit [16][17] - 1.95 - mA [16][18] - <0.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol I2C-bus Parameter Conditions Min Typ[1] Max Unit V pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3) - - VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05  VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA - - 0.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [5] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [6] VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. [7] Applies to LPC1768/67/66/65/64/63. [8] Applies to LPC1769 only. [9] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = CCLK⁄8. [10] BOD disabled. [11] On pin VDD(REG)(3V3). IBAT = 530 nA. VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aaf569 120 IDD(Reg)(3V3) (μA) 80 3.6 V 3.3 V 2.4 V 40 0 −40 −15 10 35 60 85 temperature (°C) Conditions: BOD disabled. Fig 9. Power-down mode: Typical regulator supply current IDD(Reg)(3V3) versus temperature 002aag119 1.8 Vi(VBAT) = 3.6 V 3.3 V 3.0 V 2.4 V IBAT) (μA) 1.4 1.0 0.6 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD(REG)(3V3) floating; RTC running. Fig 10.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag120 2.0 IDD(REG)(3V3)/IBAT (µA) IDD(REG)(3V3) 1.6 1.2 IBAT 0.8 0.4 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VBAT = 3.0 V; VDD(REG)(3V3) = 3.0 V; RTC running. Fig 11. Deep power-down mode: Typical regulator supply current IDD(REG)(3V3) and battery supply current IBAT versus temperature LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock PCLK = CCLK/4. Table 9.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aaf108 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 14. Typical pull-up current Ipu versus input voltage VI 002aaf109 90 Ipd (μA) 70 T = 85 °C 25 °C −40 °C 50 30 10 −10 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. Dynamic characteristics 12.1 Flash memory Table 10. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Nendu endurance tret retention time ter erase time tprog programming time Conditions [1] Min Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.3 Internal oscillators Table 12. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz [1] Parameters are valid over operating temperature range unless otherwise specified.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.5 I2C-bus Table 14. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [3][4][5][6] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.7 - s Fast-mode 1.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 18. I2C-bus pins clock timing 12.6 I2S-bus interface Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. Table 15. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to +85 C.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tf tr I2STX_CLK tWH tWL I2STX_SDA tv(Q) I2STX_WS 002aad992 tv(Q) Fig 19. I2S-bus timing (output) Tcy(clk) tf tr I2SRX_CLK tWH tWL I2SRX_SDA tsu(D) th(D) I2SRX_WS tsu(D) tsu(D) 002aae159 Fig 20. I2S-bus timing (input) LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 9.5 — 24 June 2014 © NXP Semiconductors N.V. 2014.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.7 SSP interface The maximum SSP speed is 33 Mbit/s in master mode or 8 Mbit/s in slave mode. In slave mode, the maximum SSP clock rate must be 1/12 of the SSP PCLK clock rate. Table 16. Dynamic characteristics: SSP pins in SPI mode CL = 30 pF for all SSP pins; Tamb = 40 C to 85 C; VDD(3V3) = 3.3 V to 3.6 V; input slew = 1 ns; sampled at 10 % and 90 % of the signal level. Values guaranteed by design.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 22. SSP slave timing in SPI mode LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 9.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.8 USB interface Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. Table 17. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3); 3.0 V  VDD(3V3)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.9 SPI Table 18. Dynamic characteristics of SPI pins Tamb = 40 C to +85 C. Symbol Parameter Tcy(PCLK) PCLK cycle time TSPICYC SPI cycle time tSPICLKH SPICLK HIGH time tSPICLKL SPICLK LOW time [1] Min Typ Max Unit 10 - - ns 79.6 - - ns 0.485  TSPICYC - - ns - 0.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIOH tSPIQV MOSI DATA VALID DATA VALID tSPIDSU MISO DATA VALID tSPIDH DATA VALID 002aad987 Fig 25. SPI master timing (CPHA = 0) TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tSPIOH tSPIQV MISO DATA VALID DATA VALID 002aad988 Fig 26.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TSPICYC tSPICLKH tSPICLKL SCK (CPOL = 0) SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIDH DATA VALID tSPIQV MISO tSPIOH DATA VALID DATA VALID 002aad989 Fig 27. SPI slave timing (CPHA = 0) 13. ADC electrical characteristics Table 19. ADC characteristics (full resolution) VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 20. ADC characteristics (lower resolution) Tamb = 40 C to +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC.[1] Symbol Parameter Conditions Min Typ [2][3] Max Unit ED differential linearity error - 1 - LSB EL(adj) integral non-linearity [4] - 1.5 - LSB EO offset error [5] - 2 - LSB EG gain error [6] - 2 - LSB fclk(ADC) ADC clock frequency 3.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP − VREFN 4096 002aad948 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC17xx C3 2.2 pF ADC COMPARATOR BLOCK Ri2 100 Ω - 600 Ω Ri1 2 kΩ - 5.2 kΩ AD0[n] C1 750 fF C2 65 fF Cia Rvsi VSS VEXT 002aaf197 The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are process-dependent (see Table 21). Parasitic resistance and capacitance from the pad are not included in this figure. Fig 29. ADC interface to pins AD0[n] Table 21.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Application information 15.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. If the LPC1769/68/67/66/65/64/63 VDD is always greater than 0 V while VBUS = 5 V, the VBUS pin can be connected directly to the VBUS pin on the USB connector.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD R2 R2 LPC17xx USB_UP_LED R1 1.5 kΩ R3 USB_VBUS USB-B connector USB_D+ RS = 33 Ω USB_D- RS = 33 Ω VSS aaa-008962 Fig 31. USB interface on a bus-powered device where VBUS = 5 V, VDD not present VDD(3V3) USB_UP_LED USB_CONNECT LPC17xx SoftConnect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSS 002aad939 Fig 32.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD RSTOUT RESET_N VBUS ADR/PSW ID OE_N/INT_N VDD SPEED SUSPEND LPC17xx DP 33 Ω DM 33 Ω ISP1302 VSS SCL USB_SCL Mini-AB connector SDA USB_SDA INT_N EINTn USB_D+ USB_D− USB_UP_LED 002aad941 VDD Fig 33.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD USB_UP_LED VDD USB_CONNECT LPC17xx VSS USB_D+ 33 Ω D+ USB_D− 33 Ω D− VBUS USB-B connector VBUS 002aad943 Fig 35. USB device port configuration 15.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx L XTALIN XTALOUT CL = CP XTAL RS CX2 CX1 002aaf424 Fig 37. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 23.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 15.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15.5 Reset pin configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 39. Reset pin configuration LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 9.5 — 24 June 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for part LPC1768. Table 25. ElectroMagnetic Compatibility (EMC) for part LPC1768 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm B D SOT926-1 A ball A1 index area A2 E A A1 detail X e1 e ∅v ∅w b 1/2 e C M M C A B C y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller WLCSP100: wafer level chip-scale package; 100 balls; 5.074 x 5.074 x 0.6 mm B D LPC1768UK A A2 ball A1 index area A A1 E detail X e1 1/2 e Øv Øw b e C A B C C y K e J H G F e2 E D 1/2 e C B A 1 2 3 4 5 6 7 8 9 10 ball A1 index area X 3 mm 0 scale Dimensions (mm are the original dimensions) Unit mm A A1 A2 b D E e max 0.65 0.27 0.385 0.35 5.104 5.104 nom 0.60 0.24 0.360 0.32 5.074 5.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 17. Soldering Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926-1 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.80 0.330 0.400 0.480 9.400 9.400 sot926-1_fr Fig 44.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 18. Abbreviations Table 26.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 20. Revision history Table 27. Revision history Document ID Release date Data sheet status LPC1769_68_67_66_65_64_63 v.9.5 20140624 Product data sheet Modifications: - LPC1769_68_67_66_65_64 v.9.4 SSP timing diagram updated. SSP timing parameters tv(Q), th(Q), tDS, and tDH added. See Section 12.7 “SSP interface”. • • Parameter Tj(max) added in Table 6 “Limiting values”.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 27. Revision history …continued Document ID Release date LPC1769_68_67_66_65_64_63 v.9 20120810 Product data sheet Modifications: LPC1769_68_67_66_65_64_63 v.8 Modifications: LPC1769_68_67_66_65_64_63 v.7 Modifications: Modifications: Change notice Supersedes - LPC1769_68_67_66_65_64 v.8 • Remove table note “The peak current is limited to 25 times the corresponding maximum current.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC1769/68/67/66/65/64/63 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11 11.1 11.2 11.3 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 16 17 18 19 20 21 21.1 21.2 21.3 21.4 22 23 Static characteristics. . . . . . . . . . . . . . . . . . . . Power consumption . . . . . . . . . . . . . . . . . . . . Peripheral power consumption . . . . . . . . . . . . Electrical pin characteristics . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . .