Datasheet

DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT
D
RAF
DRAFT DRAFT DRA
F
T D
RAFT DR
AFT D
DRA
F
T DRAFT DRAFT
D
RAFT
DRAFT
D
RAFT
DRA
LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 61 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
10.2 CoreMark data
Conditions: V
DD
= 3.3 V; T
amb
= 25 C; active mode; all peripherals except one UART and the SCT
disabled in the SYSAHBCLKCTRL0/1 registers; system clock derived from the IRC; system
oscillator disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision
v.4.7.
Fig 23. Active mode: CoreMark power consumption I
DD
Conditions: V
DD
= 3.3 V; active mode; all peripherals except one UART and the SCT disabled in
the SYSAHBCLKCTRL0/1 register; internal pull-up resistors enabled; BOD disabled. Measured
with Keil uVision v.4.7.
Fig 24. CoreMark score
X (X)
X XXXX
001aac984
X
X
X
X
X
X
(X)
X
<tbd>
X (X)
X XXXX
001aac984
X
X
X
X
X
X
(X)
X
<tbd>