Datasheet

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D
RAF
DRAFT DRAFT DRA
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DRA
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LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 6 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or have DMA request lines.
Fig 1. LPC15xx Block diagram
ARM
CORTEX-M3
TEST/DEBUG INTERFACE
SWD/ETM
SYSTICK
NVIC MPU
PROCESSOR CORE
PRECISION
IRC
SYSTEM
PLL
WATCHDOG
OSCILLATOR
USB
PLL
SCT
PLL
FREQUENCY
MEASUREMENT
SYSTEM
OSCILLATOR
RTC
OSCILLATOR
CLOCK
GENERATION
SCTIPU
256/128/64 kB FLASH
32 kB ROM
36/20/12 kB SRAM
4 kB EEPROM
12-bit DAC
MEMORY
PORT0/1/2
GINT0/1
PINT/
PATTERN MATCH
SCTIMER0/
PWM
SCTIMER0/
PWM
SCTIMER0/
PWM
SCTIMER0/
PWM
HS GPIO
QEI
DMA TRIGGER
ACMP0/
TEMPERATURE
SENSOR
ACMP1 ACMP2 ACMP3
INPUT MUX
SCTIMER/PWM/MOTOR CONTROL SUBSYSTEM
SPI0
USART0
SPI1
USART1
FM+ I2C0
USART2
C_CAN
FS USB/
PHY
INPUT MUX
SYSCON IOCON PMU CRC FLASH CTRL EEPROM CTRL
SYSTEM/MEMORY CONTROL
MRT RIT WWDT RTC
TIMERS
SERIAL PERIPHERALS
12-bit ADC0
TRIGGER MUX
ANALOG PERIPHERALS
12-bit ADC1
TRIGGER MUX
AHB MULTILAYER
MATRIX
AHB/APB BRIDGES
INPUT MUX INPUT MUX
DMA
pads
LPC15xx
n
pads
n
SWM
aaa-010869