Datasheet

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LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 31 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
7.21 C_CAN
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller can build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a high level of reliability.
The C_CAN functions are movable functions and are assigned to pins through the switch
matrix. Do not connect C_CAN functions to the open-drain pins PIO0_22 and PIO0_23.
7.21.1 Features
• Conforms to protocol version 2.0 parts A and B.
• Supports bit rate of up to 1 Mbit/s.
• Supports 32 Message Objects.
• Each Message Object has its own identifier mask.
• Provides programmable FIFO mode (concatenation of Message Objects).
• Provides maskable interrupts.
• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.
7.22 PWM/timer/motor control subsystem
The SCTs (State Configurable Timers) and the analog peripherals support multiple ways
of interconnecting their inputs and outputs and of interfacing to the pins and the DMA
controller. Using the highly flexible and programmable connection scheme makes it easy
to configure various subsystems for motor control and complex timing and tracking
applications. Specifically, the inputs to the SCTs and the trigger inputs of the ADCs and
DMA are selected through the input mux which offers a choice of many possible sources
for each input or trigger. SCT outputs are assigned to pins through the switch matrix
allowing for many pinout solutions.
7.22.1 PWW/timer subsystem
The SCTs can be configured to build a PWM controller with multiple outputs by
programming the MATCH and MATCHRELOAD registers of the SCTs to control the base
frequency and the duty cycle of each SCT output. More complex waveforms that span
multiple counter cycles or change behavior across or within counter cycles can be
generated using the state capability built into the SCT timers.
Combining the PWM functions with the analog functions, the PWM output can react to
control signals like comparator outputs or the ADC interrupts. The SCT IPU adds
emergency shut-down functions and pre-processing of controlling events. For an overview
of the PWM subsystem, see Figure 10 “
PWM-Analog subsystem”.
For high-speed PWM functionality, use only outputs that are fixed-pin functions to
minimize pin-to-pin differences in output skew. See also Table 22 “
SCT output dynamic
characteristics”. This reduces the number of PWM outputs to five for each large SCT.