Datasheet

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LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 20 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
7.4 EEPROM
The LPC15xx contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM
data memory. The EEPROM can be programmed using In-Application Programming (IAP)
via the on-chip boot loader software.
7.5 SRAM
The LPC15xx contain a total 36 kB, 20 kB or 12 kB of contiguous, on-chip static RAM
memory. For each SRAM configuration, the SRAM is divided into three blocks: 2 x 16 kB +
4 kB for 36 kB SRAM, 2 x 8 kB + 4 kB for 20 kB SRAM, and 2 x 4 kB + 4 kB for 12 kB
SRAM. The bottom 16 kB, 8 kB, or 4 kB are enabled by the bootloader and cannot be
disabled. The next two SRAM blocks in each configuration can be disabled or enabled
individually in the SYSCON block to save power.
U0_RXD PIO0_14 PIO0_13 PIO2_7
C_CAN mode
CAN0_TD PIO0_18 PIO0_31 PIO2_8
CAN0_RD PIO0_13 PIO0_11 PIO2_9
USB mode
USB_VBUS (same as ISP_1) PIO0_16 PIO1_11 PIO2_4
Table 6. Pin assignments for ISP modes
Boot pin LQFP48 LQFP64 LQFP100
Table 7. LPC15xx SRAM configurations
SRAM0 SRAM1 SRAM2
LPC1549/19 (total SRAM = 36 kB)
address range 0x0200 0000 to
0x0200 3FFF
0x0200 4000 to
0x0200 7FFF
0x0200 8000 to
0x0200 8FFF
size 16 kB 16 kB 4 kB
control cannot be disabled disable/enable disable/enable
default enabled enabled enabled
LPC1548/18 (total SRAM = 20 kB)
address range 0x0200 0000 to
0x0200 1FFF
0x0200 2000 to
0x0200 3FFF
0x0200 4000 to
0x0200 4FFF
size 8 kB 8 kB 4 kB
control cannot be disabled disable/enable disable/enable
default enabled enabled enabled
LPC1547/17 (total SRAM = 12 kB)
address range 0x0200 0000 to
0x0200 0FFF
0x0200 1000 to
0x0200 1FFF
0x0200 2000 to
0x0200 2FFF
size 4 kB 4 kB 4 kB
control cannot be disabled disable/enable disable/enable
default enabled enabled enabled