Datasheet

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LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 19 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
7.2 Memory Protection Unit (MPU)
The LPC15xx have a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
7.3 On-chip flash programming memory
The LPC15xx contain up to 256 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software. Flash updates via USB are supported as well.
The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
Individual pages of 256 byte each can be erased using the IAP erase page command.
7.3.1 ISP pin configuration
The LPC15xx supports ISP via the USART0, C_CAN, or USB interfaces. The ISP mode is
determined by the state of two pins (ISP_0 and ISP_1) at boot time:
The ISP pin assignment is different for each package, so that the fewest functions
possible are blocked. No more than four pins must be set aside for entering ISP in any
ISP mode. The boot code assigns two ISP pins for each package, which are probed when
the part boots to determine whether or not to enter ISP mode. Once the ISP mode has
been determined, the boot loader configures the necessary serial pins for each package.
Pins which are not configured by the boot loader for the selected boot mode (for example
CAN0_RD and CAN0_TD in USART mode) can be assigned to any function through the
switch matrix.
Table 5. ISP modes
Boot mode ISP_0 ISP_1 Description
No ISP HIGH HIGH ISP bypassed. Part attempts to boot
from flash.
C_CAN HIGH LOW Part enters ISP via C_CAN.
USB LOW HIGH Part enters ISP via USB.
USART0 LOW LOW Part enters ISP via USART0.
Table 6. Pin assignments for ISP modes
Boot pin LQFP48 LQFP64 LQFP100
ISP_0 PIO0_4 PIO1_9 PIO2_5
ISP_1 PIO0_16 PIO1_11 PIO2_4
USART mode
U0_TXD PIO0_15 PIO0_18 PIO2_6