Datasheet
DRAFT
DRAFT DRAFT DR
DRAFT DRAFT DRAFT
D
RAF
DRAFT DRAFT DRA
F
T D
RAFT DR
AFT D
DRA
F
T DRAFT DRAFT
D
RAFT
DRAFT
D
RAFT
DRA
LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 16 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin includes a 10 ns on/off
glitch filter. By default, the glitch filter is turned on.
[3] This pin is not 5 V tolerant due to special analog functionality. When configured for a digital function, this pin is 3 V tolerant
and provides
standard digital I/O functions with configurable internal pull-up and pull-down resistors and hysteresis. When configured for DAC_OUT,
the digital section of the pin is disabled and this pin is a 3 V tolerant analog output. This pin includes a 10 ns on/off glitch filter. By default,
the glitch filter is turned on.
[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, and configurable hysteresis. This pin
includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. This pin is powered in deep power-down mode and can wake
up the part.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[6] 5 V tolerant pad. RESET
functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.
[7] I
2
C-bus pins compliant with the I
2
C-bus specification for I
2
C standard mode, I
2
C Fast-mode, and I
2
C Fast-mode Plus.
[8] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
V
DDA
16 20 30 - Analog supply voltage. V
DD
and the analog reference
voltages VREFP_ADC and VREFP_DAC_VDDCMP must
not exceed the voltage level on V
DDA
. V
DDA
should typically
be the same voltages as V
DD
but should be isolated to
minimize noise and error. V
DDA
should be tied to V
DD
if the
ADC is not used.
V
DD
39,
27,
42
22,
52,
37,
57
4,
32,
70,
83,
57,
89
- 3.3 V supply voltage (2.4 V to 3.6 V). The voltage level on
V
DD
must be equal or lower than the analog supply
voltage V
DDA
.
VREFP_DAC_VDDCMP 14 18 27
[9]
- DAC positive reference voltage and analog comparator
reference voltage. The voltage level on
VREFP_DAC_VDDCMP must be equal to or lower than
the voltage applied to V
DDA
.
VREFN 11 14 22 - ADC and DAC negative voltage reference. If the ADC is
not used, tie VREFN to V
SS
.
VREFP_ADC 10 13 21 - ADC positive reference voltage. The voltage level on
VREFP_ADC must be equal to or lower than the voltage
applied to V
DDA
. If the ADC is not used, tie VREFP_ADC
to V
DD
.
V
SSA
17 21 31 - Analog ground. V
SSA
should typically be the same voltage
as V
SS
but should be isolated to minimize noise and error.
V
SSA
should be tied to V
SS
if the ADC is not used.
V
SS
41,
20,
40
56,
26,
27,
55
88,
7,
39,
40,
68,
87
- Ground.
Table 3. Pin description
Symbol
LQFP48
LQFP64
LQFP100
Reset
state
[1]
Type Description