Datasheet

DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT
D
RAF
DRAFT DRAFT DRA
F
T D
RAFT DR
AFT D
DRA
F
T DRAFT DRAFT
D
RAFT
DRAFT
D
RAFT
DRA
LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 13 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
RESET/PIO0_21 34 45 71
[6]
I; PU I RESET — External reset input: A LOW-going pulse as
short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and
processor execution to begin at address 0.
I/O PIO0_21 — General purpose port 0 input/output 21.
PIO0_22/I2C0_SCL 37 49 78
[7]
IA IO PIO0_22 — General purpose port 0 input/output 22.
I/O I2C0_SCL — I
2
C-bus clock input/output. High-current sink
if I
2
C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_23/I2C0_SDA 38 50 79
[7]
IA IO PIO0_23 — General purpose port 0 input/output 23.
I/O I2C0_SDA — I2C-bus data input/output. High-current sink
if I2C Fast-mode Plus is selected in the I/O configuration
register.
PIO0_24/SCT0_OUT6 43 58 90
[8]
I; PU IO PIO0_24 — General purpose port 0 input/output 24.
High-current output driver.
O SCT0_OUT6 — SCTimer0/PWM output 6.
PIO0_25/ACMP0_I4 44 60 93
[2]
I; PU IO PIO0_25 — General purpose port 0 input/output 25.
A ACMP0_I4 — Analog comparator 0 input 4.
PIO0_26/ACMP0_I3/
SCT3_OUT3
45 61 95
[2]
I; PU IO PIO0_26 — General purpose port 0 input/output 26.
A ACMP0_I3 — Analog comparator 0 input 3.
O SCT3_OUT3 — SCTimer3/PWM output 3.
PIO0_27/ACMP_I1 46 62 97
[2]
I; PU IO PIO0_27 — General purpose port 0 input/output 27.
A ACMP_I1 — Analog comparator common input 1.
PIO0_28/ACMP1_I3 47 63 98
[2]
I; PU IO PIO0_28 — General purpose port 0 input/output 28.
A ACMP1_I3 — Analog comparator 1 input 3.
PIO0_29/ACMP2_I3/
SCT2_OUT4
48 64 100
[2]
I; PU IO PIO0_29 — General purpose port 0 input/output 29.
A ACMP2_I3 — Analog comparator 2 input 3.
O SCT2_OUT4 — SCTimer2/PWM output 4.
PIO0_30/ADC0_11 -11
[2]
I; PU IO PIO0_30 — General purpose port 0 input/output 30.
A ADC0_11 — ADC0 input 11.
PIO0_31/ADC0_9 -33
[2]
I; PU IO PIO0_31 — General purpose port 0 input/output 31.
On the LQFP64 package, this pin is assigned to
CAN0_TD in ISP C_CAN mode.
A ADC0_9 — ADC0 input 9.
PIO1_0/ADC0_8 -45
[2]
I; PU IO PIO1_0 — General purpose port 1 input/output 0.
A ADC0_8 — ADC0 input 8.
PIO1_1/ADC1_0 -1523
[2]
I; PU IO PIO1_1 — General purpose port 1 input/output 1.
A ADC1_0 — ADC1 input 0.
PIO1_2/ADC1_4 -2536
[2]
I; PU IO PIO1_2 — General purpose port 1 input/output 2.
A ADC1_4 — ADC1 input 4.
Table 3. Pin description
Symbol
LQFP48 LQFP64 LQFP100
Reset
state
[1]
Type Description