Datasheet

DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT
D
RAF
DRAFT DRAFT DRA
F
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RAFT DR
AFT D
DRA
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LPC15xx All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Objective data sheet Rev. 1.0 — 16 January 2014 48 of 98
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
In addition, ISP entry the external pins can be disabled without enabling CRP. For details,
see the LPC15xx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected, fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using ISP
pin as well. If necessary, the application must provide a flash update mechanism
using IAP calls or using a call to the reinvoke ISP command to enable flash update via
the USART.
In addition to the three CRP levels, sampling of the ISP pins for valid user code can be
disabled. For details, see the LPC15xx user manual.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.