Datasheet

LPC1315_16_17_45_46_47 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 20 September 2012 58 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
Fig 26. SSP slave timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
T
cy(clk)
t
clk(H)
t
clk(L)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID
DATA VALID
MOSI
MISO
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
CPHA = 1
CPHA = 0
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