Datasheet

LPC1315_16_17_45_46_47 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 20 September 2012 5 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
(1) Available on LQFP48 and LQFP64 packages only.
(2) CT16B0_CAP1, CT16B1_CAP1, CT32B1_CAP1 inputs available on LQFP64 packages only. CT32B0_CAP0 input available on
LQFP48 and LQFP64 packages only.
Fig 1. Block diagram
SRAM
8/10/12 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
RESET
SWD, JTAG
LPC1315/16/17
LPC1345/46/47
slave
slave
FLASH
32/48/64 kB
EEPROM
2/4 kB
slaveslave
ROM
16 kB
slave
AHB-LITE BUS
GPIO ports 0/1
CLKOUT
IRC, WDO
SYSTEM OSCILLATOR
POR
PLL0 USB PLL
BOD
12-bit ADC
USART/
SMARTCARD INTERFACE
AD[7:0]
RXD
TXD
CTS, RTS, DTR
SCLK
GPIO PIN INTERRUPT
32-bit COUNTER/TIMER 0
CT32B0_MAT[3:0]
CT32B0_CAP[1:0]
(2)
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
CT32B1_CAP[1:0]
(2)
DCD , DSR
(1)
, RI
(1)
16-bit COUNTER/TIMER 1
WINDOWED WATCHDOG
TIMER
GPIO GROUP0 INTERRUPT
CT16B1_MAT[1:0]
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
CT16B0_CAP[1:0]
(2)
CT16B1_CAP[1:0]
(2)
GPIO pins
GPIO pins
GPIO GROUP1 INTERRUPT
GPIO pins
system bus
SSP0
SCK0, SSEL0,
MISO0, MOSI0
SSP1
SCK1, SSEL1,
MISO1, MOSI1
I
2
C-BUS
IOCON
SYSTEM CONTROL
PMU
RI TIMER
SCL, SDA
XTALIN XTALOUT
USB DEVICE
CONTROLLER
(LPC1345/46/47)
USB_DP
USB_DM
USB_VBUS
USB_FTOGGLE,
USB_CONNECT
002aag241
master
slave