Datasheet
LPC1315_16_17_45_46_47 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 20 September 2012 31 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
7.17.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (T
cy(WDCLK)
256 4) to (T
cy(WDCLK)
2
24
4) in
multiples of T
cy(WDCLK)
4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the watchdog
oscillator (WDO). This gives a wide range of potential timing choices of watchdog
operation under different power conditions.
7.18 Clocking and power control
7.18.1 Integrated oscillators
The LPC1315/16/17/45/46/47 include three independent oscillators. These are the
system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each
oscillator can be used for more than one purpose as required in a particular application.
Following reset, the LPC1315/16/17/45/46/47 will operate from the internal RC oscillator
until switched by software. This allows systems to operate without any external crystal and
the bootloader code to operate at a known frequency.
See Figure 9
for an overview of the LPC1315/16/17/45/46/47 clock generation.