Datasheet

Product data sheet Rev. 3 — 20 September 2012 30 of 77

NXP Semiconductors

LPC1315/16/17/45/46/47

32-bit ARM Cortex-M3 microcontroller

7.14.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse-width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

7.15 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 48-bit counter which is compared to

a selectable value, generating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.15.1 Features

• 48-bit counter running from the main clock. Counter can be free-running or can be

reset when an RIT interrupt is generated.

• 48-bit compare value.

• 48-bit compare mask. An interrupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

• Support for ETM timestamp generator.

7.16 System tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.17 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.