Datasheet
LPC1315_16_17_45_46_47 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 20 September 2012 29 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.12.1 Features
• The I
2
C-interface is an I
2
C-bus compliant interface with open-drain pins. The I
2
C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I
2
C-bus can be used for test and diagnostic purposes.
• The I
2
C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 12-bit ADC
The LPC1315/16/17/45/46/47 contains one ADC. It is a single 12-bit successive
approximation ADC with eight channels.
7.13.1 Features
• 12-bit successive approximation ADC.
• Input multiplexing among 8 pins and three internal sources.
• Low-power mode.
• 10-bit double-conversion rate mode (conversion rate of up to 1 Msample/s).
• Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage
level).
• 12-bit conversion rate of up to 500 kHz.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• On the LQFP64 package, power and reference pins (V
DDA
, V
SSA
, VREFP, VREFN)
are brought out on separate pins for superior noise immunity.
7.14 General purpose external event counter/timers
The LPC1315/16/17/45/46/47 includes two 32-bit counter/timers and two 16-bit
counter/timers. The counter/timer is designed to count cycles of the system derived clock.
It can optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. Each counter/timer also includes one capture input to trap
the timer value when an input signal transitions, optionally generating an interrupt.